diff options
| author | Jim Lawson | 2019-02-21 13:13:13 -0800 |
|---|---|---|
| committer | mergify[bot] | 2019-02-21 21:13:13 +0000 |
| commit | b3833821a50eb7b08fe75f3729ef57355d5765ec (patch) | |
| tree | b0d2d38b408b06219539b7be344d6829ec2a79c6 /src/main | |
| parent | ad0c4ce7afc9856c127031a582232330276bdafe (diff) | |
Don't let the main module become deduped out of existence. (#1023)
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/Dedup.scala | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala index 56ea7cf8..83daad7f 100644 --- a/src/main/scala/firrtl/transforms/Dedup.scala +++ b/src/main/scala/firrtl/transforms/Dedup.scala @@ -373,13 +373,17 @@ object DedupModules { val iGraph = new InstanceGraph(circuit) (iGraph.moduleMap, iGraph.moduleOrder.reverse) } - val top = CircuitTarget(circuit.main) - + val main = circuit.main + val top = CircuitTarget(main) val (tag2all, tagMap) = buildRTLTags(top, moduleLinearization, noDedups, annotations) // Set tag2name to be the best dedup module name val moduleIndex = circuit.modules.zipWithIndex.map{case (m, i) => m.name -> i}.toMap - def order(l: String, r: String): String = if (moduleIndex(l) < moduleIndex(r)) l else r + def order(l: String, r: String): String = { + if (l == main) l + else if (r == main) r + else if (moduleIndex(l) < moduleIndex(r)) l else r + } // Maps a module's tag to its deduplicated module val tag2name = mutable.HashMap.empty[String, String] |
