Don't let the main module become deduped out of existence. (#1023)

2 files changed, 28 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/transforms/Dedup.scala b/src/main/scala/firrtl/transforms/Dedup.scala
index 56ea7cf8..83daad7f 100644
--- a/src/main/scala/firrtl/transforms/Dedup.scala
+++ b/src/main/scala/firrtl/transforms/Dedup.scala
@@ -373,13 +373,17 @@ object DedupModules {
       val iGraph = new InstanceGraph(circuit)
       (iGraph.moduleMap, iGraph.moduleOrder.reverse)
     }
-    val top = CircuitTarget(circuit.main)
-
+    val main = circuit.main
+    val top = CircuitTarget(main)
     val (tag2all, tagMap) = buildRTLTags(top, moduleLinearization, noDedups, annotations)
 
     // Set tag2name to be the best dedup module name
     val moduleIndex = circuit.modules.zipWithIndex.map{case (m, i) => m.name -> i}.toMap
-    def order(l: String, r: String): String = if (moduleIndex(l) < moduleIndex(r)) l else r
+    def order(l: String, r: String): String = {
+      if (l == main) l
+      else if (r == main) r
+      else if (moduleIndex(l) < moduleIndex(r)) l else r
+    }
 
     // Maps a module's tag to its deduplicated module
     val tag2name = mutable.HashMap.empty[String, String]
diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index d4fe54a1..9b949274 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -532,5 +532,26 @@ class DedupModuleTests extends HighTransformSpec {
     cs.annotations.toSeq should not contain (SingleTargetDummyAnnotation(A.ref("x")))
     cs.deletedAnnotations.isEmpty should be (true)
   }
+  "main" should "not be deduped even if it's the last module" in {
+    val input =
+      """circuit main:
+        |  module dupe:
+        |    input in: UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+        |  module main:
+        |    input in:  UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+      """.stripMargin
+    val check =
+      """circuit main:
+        |  module main:
+        |    input in:  UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+      """.stripMargin
+    execute(input, check, Seq.empty)
+  }
 }