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| author | Schuyler Eldridge | 2019-02-05 11:23:19 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-02-05 14:09:42 -0500 |
| commit | a77122b4bb8756636c169473af3dc367b14698ef (patch) | |
| tree | 318e35fb1d2e7aa503ab7cff56d9169a9cdf4e99 /src/main | |
| parent | 6ef7ad148ff491c06d417d417e2134da7ff49ef7 (diff) | |
Add RemoveValidIf to -X mverilog
This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization
Transform. A test case is included to verify that `is invalid` is
properly converted to a connection to zero.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/LoweringCompilers.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala index 7499d6d1..9969150d 100644 --- a/src/main/scala/firrtl/LoweringCompilers.scala +++ b/src/main/scala/firrtl/LoweringCompilers.scala @@ -119,6 +119,7 @@ class MinimumLowFirrtlOptimization extends CoreTransform { def inputForm = LowForm def outputForm = LowForm def transforms = Seq( + passes.RemoveValidIf, passes.Legalize, passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter passes.SplitExpressions) |