From a77122b4bb8756636c169473af3dc367b14698ef Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Tue, 5 Feb 2019 11:23:19 -0500
Subject: Add RemoveValidIf to -X mverilog

This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization
Transform. A test case is included to verify that `is invalid` is
properly converted to a connection to zero.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 src/main/scala/firrtl/LoweringCompilers.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/main')

diff --git a/src/main/scala/firrtl/LoweringCompilers.scala b/src/main/scala/firrtl/LoweringCompilers.scala
index 7499d6d1..9969150d 100644
--- a/src/main/scala/firrtl/LoweringCompilers.scala
+++ b/src/main/scala/firrtl/LoweringCompilers.scala
@@ -119,6 +119,7 @@ class MinimumLowFirrtlOptimization extends CoreTransform {
   def inputForm = LowForm
   def outputForm = LowForm
   def transforms = Seq(
+    passes.RemoveValidIf,
     passes.Legalize,
     passes.memlib.VerilogMemDelays, // TODO move to Verilog emitter
     passes.SplitExpressions)
-- 
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