diff options
| author | Jack Koenig | 2019-01-02 17:37:18 -0800 |
|---|---|---|
| committer | Jack Koenig | 2019-01-02 17:37:18 -0800 |
| commit | 8bc25bbc0ff998565afd153a44bf8f11316ba0f0 (patch) | |
| tree | 0465949193ce089197f88640968fda02408e05c5 /src/main | |
| parent | 4253791132c5c550e1bc4a8070cb54e558f17809 (diff) | |
Make GroupComponents run ResolveKinds
This fixes an issue where expressions created by GroupComponents would
be improperly lowered because they were not marked as references to
instance ports.
Diffstat (limited to 'src/main')
| -rw-r--r-- | src/main/scala/firrtl/transforms/GroupComponents.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/GroupComponents.scala b/src/main/scala/firrtl/transforms/GroupComponents.scala index 55828e0a..805b534e 100644 --- a/src/main/scala/firrtl/transforms/GroupComponents.scala +++ b/src/main/scala/firrtl/transforms/GroupComponents.scala @@ -4,7 +4,7 @@ import firrtl._ import firrtl.Mappers._ import firrtl.ir._ import firrtl.annotations.{Annotation, ComponentName} -import firrtl.passes.{InferTypes, LowerTypes, MemPortUtils} +import firrtl.passes.{InferTypes, LowerTypes, MemPortUtils, ResolveKinds} import firrtl.Utils.kind import firrtl.graph.{DiGraph, MutableDiGraph} @@ -62,7 +62,7 @@ class GroupComponents extends firrtl.Transform { case other => Seq(other) } val cs = state.copy(circuit = state.circuit.copy(modules = newModules)) - val csx = InferTypes.execute(cs) + val csx = ResolveKinds.execute(InferTypes.execute(cs)) csx } |
