| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz | |
| * Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before) | |||
| 2016-02-09 | Added license to FIRRTL files | azidar | |
| 2016-01-28 | Changed mod to rem | azidar | |
| 2015-08-25 | Removed IntWidth, now only use LongWidth. Now do width inference for ↵ | azidar | |
| Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt | |||
| 2015-08-20 | Added Poison node. Includes tests. #26. | azidar | |
| 2015-08-19 | Switched to new bigint library | azidar | |
| 2015-08-04 | Added verilog keywords to uniquify them | azidar | |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar | |
| invalid <> assignments. | |||
| 2015-07-30 | Added module name to error messages. | azidar | |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar | |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar | |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz | |
| 2015-07-14 | Added clock support | azidar | |
| 2015-07-14 | Updated flo backend | azidar | |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar | |
| 2015-06-04 | Fixed fir files so they correctly compile to verilog! Front-end needs to ↵ | azidar | |
| generate as-SInt instead of convert, always. Added fast build to Makefile | |||
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ↵ | azidar | |
| low-firrtl syntax. Generates verilog that compiles, but is not correct | |||
| 2015-06-02 | merge + fix trim to use correct bits operands | jackbackrack | |
| 2015-05-29 | fix concat, as-sint, turn off temp-elimination | jackbackrack | |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ↵ | azidar | |
| smem. Added firrtl-gensym utility to generate a hashmap of names | |||
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ↵ | azidar | |
| instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed | |||
| 2015-05-21 | fix pad/trim pass and fix bug in bits-select width inference | jackbackrack | |
| 2015-05-21 | Added pad pass, used for flo backend | azidar | |
| 2015-05-20 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar | |
| 2015-05-20 | fix writeport emission for flo | jackbackrack | |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops ↵ | azidar | |
| strict. Have not tested this | |||
| 2015-05-19 | get flo backend running again with no pads and generic operators | jackbackrack | |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be ↵ | azidar | |
| flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters | |||
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable ↵ | azidar | |
| plugging in other backends. Also updated a lot of tests, but not all of them because its annoying. | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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