Added verilog keywords to uniquify them

1 files changed, 1 insertions, 1 deletions

diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index 812a917e..7ef942f2 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -198,7 +198,7 @@ defn emit-module (m:InModule,sh:HashTable<Symbol,Int>) :
 
 public defn emit-flo (with-output:(() -> False) -> False, c:Circuit) :
    with-output $ {
-      emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule,v-keywords))
+      emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule))
       false
       }
    c