merge + fix trim to use correct bits operands

1 files changed, 13 insertions, 9 deletions

diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index c75071cd..bb9365ae 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -24,9 +24,11 @@ defn set-width (desired:Int,t:Type) -> Type :
 
 defn pad-widths-e (desired:Int,e:Expression) -> Expression :
    defn trim (desired:Int, e:Expression) :
-     DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e)))
+     ;; println-all(["TRIM " desired " e " e])
+     DoPrim(BITS-SELECT-OP,list(e),list(desired - 1, 0),set-width(desired,type(e)))
    defn pad (desired:Int, e:Expression) :
-     DoPrim(PAD-OP,list(e),list(),set-width(desired,type(e)))
+     ;; println-all(["PAD " desired " e " e])
+     DoPrim(PAD-OP,list(e),list(desired),set-width(desired,type(e)))
    defn trim-pad (desired:Int, e:Expression) :
      val i = int-width!(type(e))
      if i > desired : trim(desired, e)
@@ -83,7 +85,9 @@ defn pad-widths-s (s:Stmt) -> Stmt :
 public defn pad-widths (c:Circuit) -> Circuit :
    Circuit{info(c),_,main(c)} $
       for m in modules(c) map :
-         Module(info(m),name(m),ports(m),pad-widths-s(body(m)))
+         match(m) :
+            (m:ExModule) : error("Cannot use flo backend with external modules")
+            (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m)))
 
 ;============= Flo Backend ================
 
@@ -217,7 +221,7 @@ defn maybe-mov (e:Expression) -> String :
       (e) :           false
    if need-mov?: "mov " else: ""
 
-defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol) :
+defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol,sh:HashTable<Symbol,Int>) :
    match(s) :
       (s:DefWire) : ""
       (s:DefInstance) : error("Shouldn't be here")
@@ -226,7 +230,7 @@ defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol) :
          emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top)
       (s:DefNode) :
          emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top)
-      (s:Begin) : do(emit-s{_, v, top}, body(s))
+      (s:Begin) : do(emit-s{_, v, top,sh}, body(s))
       (s:Connect) : 
          match(loc(s)) :
            (r:Ref) :
@@ -236,14 +240,14 @@ defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol) :
              else :
                 emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top)
            (w:WritePort) :
-             val n = firrtl-gensym(`F)
+             val n = firrtl-gensym(`F,sh)
              emit-all([top "::" n " = wr'" prim-width(type(w)) " " enable(w) " " mem(w) " " index(w) " " exp(s) "\n"], top)
            (o) :
              println-all(["CONNEcT LOC " loc(s)])
              error("Unknown Connect")
       (s) : s 
 
-defn emit-module (m:Module) :
+defn emit-module (m:InModule,sh:HashTable<Symbol,Int>) :
    val v = Vector<Symbol>()
    for port in ports(m) do :
       if name(port) ==`reset :
@@ -251,10 +255,10 @@ defn emit-module (m:Module) :
       else : switch {_ == direction(port)} :
          INPUT : print-all([name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"])
          OUTPUT : add(v,name(port))
-   emit-s(body(m), to-list(v), name(m))
+   emit-s(body(m), to-list(v), name(m),sh)
 
 public defn emit-flo (file:String, c:Circuit) :
    with-output-file{file, _} $ fn () :
-      emit-module(modules(c)[0])
+      emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule))
       false
    c