From a2a48576534f87b28566504bb1e0c7faa493f463 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 27 May 2015 15:43:15 -0700 Subject: Added external modules. Switched lower firrtl back to wire r; r := Register, instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed --- src/main/stanza/flo.stanza | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'src/main/stanza/flo.stanza') diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index e870d7ed..0f1f4eeb 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -32,15 +32,15 @@ defn pad-widths-e (desired:Int,e:Expression) -> Expression : if i > desired : DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e))) else if i == desired : e* - else : DoPrim(PAD-OP,list(e*),list(),set-width(desired,type(e*))) + else : DoPrim(PAD-OP,list(e*),list(desired),set-width(desired,type(e*))) else : e - (e:WRef|WSubfield|WIndex) : + (e:WRef|WSubfield|WIndex|Register|ReadPort) : println(e) val i = int-width!(type(e)) if i > desired : DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e))) else if i == desired : e - else : DoPrim(PAD-OP,list(e),list(),set-width(desired,type(e))) + else : DoPrim(PAD-OP,list(e),list(desired),set-width(desired,type(e))) (e:UIntValue) : val i = int-width!(type(e)) if i > desired : @@ -64,7 +64,9 @@ defn pad-widths-s (s:Stmt) -> Stmt : public defn pad-widths (c:Circuit) -> Circuit : Circuit{info(c),_,main(c)} $ for m in modules(c) map : - Module(info(m),name(m),ports(m),pad-widths-s(body(m))) + match(m) : + (m:ExModule) : error("Cannot use flo backend with external modules") + (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m))) ;============= Flo Backend ================ @@ -224,7 +226,7 @@ defn emit-s (s:Stmt, v:List, top:Symbol) : error("Unknown Connect") (s) : s -defn emit-module (m:Module) : +defn emit-module (m:InModule) : val v = Vector() for port in ports(m) do : if name(port) ==`reset : @@ -236,6 +238,6 @@ defn emit-module (m:Module) : public defn emit-flo (file:String, c:Circuit) : with-output-file{file, _} $ fn () : - emit-module(modules(c)[0]) + emit-module(modules(c)[0] as InModule) false c -- cgit v1.2.3 From b44b49e6a6589add30b5b1d89d85f2e20432a515 Mon Sep 17 00:00:00 2001 From: azidar Date: Wed, 27 May 2015 17:15:44 -0700 Subject: Added sequential memories. mem no longer exists, must declare either cmem or smem. Added firrtl-gensym utility to generate a hashmap of names --- src/main/stanza/flo.stanza | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/main/stanza/flo.stanza') diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index 0f1f4eeb..41de8f82 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -200,7 +200,7 @@ defn maybe-mov (e:Expression) -> String : (e) : false if need-mov?: "mov " else: "" -defn emit-s (s:Stmt, v:List, top:Symbol) : +defn emit-s (s:Stmt, v:List, top:Symbol,sh:HashTable) : match(s) : (s:DefWire) : "" (s:DefInstance) : error("Shouldn't be here") @@ -209,7 +209,7 @@ defn emit-s (s:Stmt, v:List, top:Symbol) : emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top) (s:DefNode) : emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top) - (s:Begin) : do(emit-s{_, v, top}, body(s)) + (s:Begin) : do(emit-s{_, v, top,sh}, body(s)) (s:Connect) : match(loc(s)) : (r:Ref) : @@ -219,14 +219,14 @@ defn emit-s (s:Stmt, v:List, top:Symbol) : else : emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top) (w:WritePort) : - val n = firrtl-gensym(`F) + val n = firrtl-gensym(`F,sh) emit-all([top "::" n " = wr'" prim-width(type(w)) " " enable(w) " " mem(w) " " index(w) " " exp(s) "\n"], top) (o) : println-all(["CONNEcT LOC " loc(s)]) error("Unknown Connect") (s) : s -defn emit-module (m:InModule) : +defn emit-module (m:InModule,sh:HashTable) : val v = Vector() for port in ports(m) do : if name(port) ==`reset : @@ -234,10 +234,10 @@ defn emit-module (m:InModule) : else : switch {_ == direction(port)} : INPUT : print-all([name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"]) OUTPUT : add(v,name(port)) - emit-s(body(m), to-list(v), name(m)) + emit-s(body(m), to-list(v), name(m),sh) public defn emit-flo (file:String, c:Circuit) : with-output-file{file, _} $ fn () : - emit-module(modules(c)[0] as InModule) + emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule)) false c -- cgit v1.2.3