merge + fix trim to use correct bits operands

57 files changed, 1491 insertions, 1393 deletions

diff --git a/Makefile b/Makefile
index 3f3322af..07184181 100644
--- a/Makefile
+++ b/Makefile
@@ -32,6 +32,12 @@ errors:
 chisel3:
 	cd $(test_dir)/chisel3 && lit -v . --path=$(root_dir)/utils/bin/
 
+features:
+	cd $(test_dir)/features && lit -v . --path=$(root_dir)/utils/bin/
+
+custom:
+	cd $(test_dir)/custom && lit -v . --path=$(root_dir)/utils/bin/ --max-time=10
+
 clean:
 	rm -f $(test_dir)/*/*/*.out
 	rm -f $(test_dir)/*/*.out
diff --git a/TODO b/TODO
index 9a03aa85..c6d6768b 100644
--- a/TODO
+++ b/TODO
@@ -3,23 +3,19 @@
 ================================================
 
 ======== Current Tasks ========
+SeqMem
+move width inference earlier
 Temp elimination needs to count # uses
 Declared references needs to understand scope <= check in high form check
-Size of vector type must be non-negative
 Check for recursively defined instances
-<>
+Names in bundles must be unique
+Fix reset scope
+Fix firrtl-gen so it is a relative pass, not global state
 Add Unit Tests for each pass
-   Separate passes into discrete chunks
-   Push all tests entirely through
    Check after each pass
    write test that checks instance types are correctly lowered
-move width inference earlier
-Remove Pad
-Fix all primops and width inference
-Verilog
-SeqMem
-BlackBoxes
 Scaling
+Do name-mangling differently, use _xEF or something like that
 
 ======== Verilog Backend Notes ========
 * 1) Emit module. No Parameters. Include clk and reset signals
@@ -35,32 +31,14 @@ o 6) Emit all register updates:
 Notes:
    For now, emit mems as reg with nothing else.
    WritePorts?
-
    
 ======== Update Core ==========
-Add exmodule
 Add vptype
 Add readwriteport
 
 ======== Check Passes ==========
-Well-formed high firrtl 
-   Unique names per module
-   No name can be a prefix of any other name.
-   No nested modules
-   Only modules in circuit (no statements or expressions)
-   Cannot connect directly to a mem ever
-   Subfields are only on bundles, before type inference 
-   Can only connect to a Ref or Subfield or Index
-   UInt only has positive ints
+High-Firrtl
    No combinational loops
-   cannot connect to a pad, or a register. only connct to a reference
-   onreset can only handle a register
-   all references are declared
-   expression in pad must be a ground type
-   node's value cannot be a bundle with a flip in it
-   mems cannot be a bundle with flips
-   2nd arg in dshr/l must be UInt
-   pred in conditionally must be of type UInt
 After adding dynamic assertions, insert bounds check with accessor expansion
 Well-formed low firrtl
    All things only assigned to once
@@ -71,19 +49,13 @@ Width inference
    Pad's width is greater than value's width
    pad's width is greater than value's width
    connect can connect from big to small??
-Check Gender
 
 ======== Other Passes ========
-; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
-; CHECK: Done!
-
 constant folding (partial eval) pass
    Get rid of unnecessary pads
    push pad into literal
 common subexpression elimination pass
 deadcode elimination
-Verilog backend
-Eliminate skips
 
 ======== Consultations ========
 Andrew: Way to keep Array information for backends to avoid code explosion
diff --git a/spec/spec.pdf b/spec/spec.pdf
index 504a511b..48719e1c 100644
--- a/spec/spec.pdf
+++ b/spec/spec.pdf
diff --git a/src/lib/stanza.zip b/src/lib/stanza.zip
index aed19c22..8dc3ea0a 100644
--- a/src/lib/stanza.zip
+++ b/src/lib/stanza.zip
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 8b84cc54..0c3978ab 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -12,7 +12,7 @@ public defstruct StandardFlo <: Compiler :
    file: String with: (as-method => true)
 public defmethod passes (c:StandardFlo) -> List<Pass> :
    to-list $ [
-      CheckHighForm()
+      CheckHighForm(expand-delin)
       ;; TempElimination()
       ToWorkingIR()
       MakeExplicitReset()
@@ -31,6 +31,9 @@ public defmethod passes (c:StandardFlo) -> List<Pass> :
       Inline()
       SplitExp()
       ToRealIR()
+      SpecialRename(`#,`_)
+      SpecialRename(`$,`::)
+      CheckHighForm(`::)
       Flo(file(c))
    ]
 
@@ -38,8 +41,13 @@ public defstruct StandardVerilog <: Compiler :
    file: String with: (as-method => true)
 public defmethod passes (c:StandardVerilog) -> List<Pass> :
    to-list $ [
+<<<<<<< HEAD
       CheckHighForm()
       ;; TempElimination()
+=======
+      CheckHighForm(expand-delin)
+      TempElimination()
+>>>>>>> upstream/master
       ToWorkingIR()
       MakeExplicitReset()
       ResolveKinds()
@@ -53,9 +61,9 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       ExpandIndexedConnects()
       ExpandWhens()
       InferWidths()
-      ;Inline()
       SplitExp()
       ToRealIR()
+      SpecialRename(`#,`_)
       Verilog(file(c))
    ]
 
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
new file mode 100644
index 00000000..1ca29bdd
--- /dev/null
+++ b/src/main/stanza/custom-compiler.stanza
@@ -0,0 +1,38 @@
+defpackage firrtl/custom-compiler :
+   import core
+   import verse
+   import firrtl/ir-utils
+   import firrtl/ir2
+   import firrtl/passes
+   import firrtl/errors
+   import firrtl/verilog
+   import firrtl/custom-passes
+
+public defstruct InstrumentedVerilog <: Compiler :
+   file: String with: (as-method => true)
+   args: List<String>
+public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
+   to-list $ [
+      WhenCoverage(args(c)[0],args(c)[1])
+      CheckHighForm(expand-delin)
+      TempElimination()
+      ToWorkingIR()
+      MakeExplicitReset()
+      ResolveKinds()
+      CheckKinds()
+      InferTypes()
+      CheckTypes()
+      ResolveGenders()
+      CheckGenders()
+      ExpandAccessors()
+      LowerToGround()
+      ExpandIndexedConnects()
+      ExpandWhens()
+      InferWidths()
+      SplitExp()
+      ToRealIR()
+      SpecialRename(`#,`_)
+      Verilog(file(c))
+   ]
+
+
diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza
new file mode 100644
index 00000000..e4c3d9d3
--- /dev/null
+++ b/src/main/stanza/custom-passes.stanza
@@ -0,0 +1,106 @@
+defpackage firrtl/custom-passes :
+   import core
+   import verse
+   import firrtl/ir-utils
+   import firrtl/ir2
+
+public defstruct WhenCoverage <: Pass :
+   port-name : String
+   reg-name : String
+public defmethod pass (b:WhenCoverage) -> (Circuit -> Circuit) : when-coverage{port-name(b),reg-name(b),_}
+public defmethod name (b:WhenCoverage) -> String : "When Coverage"
+public defmethod short-name (b:WhenCoverage) -> String : "when-coverage"
+
+;============ Utilz =============
+defn concat-all (ls:List<Expression>) -> Expression :
+   if length(ls) == 0 : error("Shouldn't be here")
+   if length(ls) == 1 : head(ls)
+   else : DoPrim( CONCAT-OP,
+                  list(head(ls),concat-all(tail(ls))),
+                  list(),
+                  UIntType(UnknownWidth()))
+
+;============ When Coverage Pass =============
+;port width = 1 bit per scope + portwidths of all instances
+
+defn needs-instrumentation (m:Module,ms:List<Module>,instrument?:HashTable<Symbol,True|False>) -> False :
+   defn needs-instrumentation-s (s:Stmt) -> False :
+      match(s) :
+         (s:Conditionally) :instrument?[name(m)] = true
+         (s:DefInstance) : 
+            val module-of-inst = for x in ms find : name(x) == name(module(s) as Ref)
+            if module-of-inst != false : 
+               needs-instrumentation(module-of-inst as Module,ms,instrument?)
+               instrument?[name(m)] = instrument?[name(module-of-inst as Module)]
+         (s) : false
+      do(needs-instrumentation-s,s)
+
+   match(m) : 
+      (m:InModule) : do(needs-instrumentation-s,body(m))
+      (m:ExModule) : false
+   
+defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Symbol,True|False>, m:InModule) -> InModule :
+   val when-bits = Vector<Ref>()
+   val inst-bits = Vector<Ref>()
+   val sym = HashTable<Symbol,Int>(symbol-hash)
+   val w1 = IntWidth(1)
+   val t1 = UIntType(w1)
+   val u1 = UIntValue(1,w1)
+   defn when-coverage (s:Stmt) -> Stmt :
+      match(s) :
+         (s:Conditionally) : 
+            val ref = Ref(firrtl-gensym(reg-name,sym),t1)
+            add(when-bits,ref)
+            val conseq* = Begin(list(Connect(FileInfo()ref,u1),conseq(s)))
+            map(when-coverage,Conditionally(info(s),pred(s),conseq*,alt(s)))
+         (s:DefInstance) : 
+            if instrument?[name(module(s) as Ref)] :
+               val ref = Ref(firrtl-gensym(port-name,sym),UIntType(UnknownWidth()))
+               add(inst-bits,ref)
+               val sfld = Subfield(Ref(name(s),UnknownType()),port-name,UnknownType())
+               Begin(list(s,Connect(FileInfo(),ref,sfld)))
+            else : s
+         (s) : map(when-coverage,s)
+
+   val body* = when-coverage(body(m))
+   val logic = Vector<Stmt>()
+   val port-ref = Ref(port-name,UIntType(UnknownWidth()))
+
+   val w-ls = to-list $ when-bits
+   if length(w-ls) != 0 :
+      val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
+      add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref))
+      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(0,IntWidth(length(w-ls))))
+      for (x in w-ls, i in 0 to false) do :
+         add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
+         add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1)))
+      add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls))
+
+   val i-ls = to-list $ inst-bits
+   if length(i-ls) != 0 :
+      for (x in i-ls, i in 0 to false) do :
+         add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
+         add{logic,_} $ Connect(FileInfo(),x,UIntValue(0,UnknownWidth()))
+
+   if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls)))
+
+   if length(logic) != 0 :
+      val ports* = List(Port(FileInfo(),port-name,OUTPUT,UIntType(UnknownWidth())),ports(m))
+      val body** = Begin(list(Begin(to-list $ logic),body*))
+      InModule(info(m),name(m),ports*,body**)
+   else : m
+
+public defn when-coverage (port-name:String, reg-name:String, c:Circuit) :
+   val instrument? = HashTable<Symbol,True|False>(symbol-hash)
+   for m in modules(c) do :
+      instrument?[name(m)] = false
+   val top = for m in modules(c) find : name(m) == main(c)
+   if top != false : needs-instrumentation(top as Module,modules(c),instrument?)
+
+   val modules* = for m in modules(c) map :
+      match(m) :
+         (m:InModule) : 
+            when-coverage(to-symbol $ port-name,to-symbol $ reg-name,instrument?,m)
+         (m:ExModule) : m
+   Circuit(info(c),modules*,main(c))
+
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 8c5532b0..0795a2a9 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -19,7 +19,6 @@ defpackage firrtl/errors :
 ; o No names
 ; o No Unknowns
 ; o All widths are positive
-; o Pad's width is greater than value's width
 ; o pad's width is greater than value's width
 ; o widths are large enough to contain value
 
@@ -43,9 +42,13 @@ defpackage firrtl/errors :
 ; * No name can be a prefix of any other name.
 ; * all references are declared
 ; * UInt only has positive ints
+; * Vector types has positive size
+; * Width sizes are positive
+; * Primops have the correct number of arguments
 
-public defstruct CheckHighForm <: Pass
-public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form
+public defstruct CheckHighForm <: Pass :
+   sym : Symbol
+public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form{_,sym(b)}
 public defmethod name (b:CheckHighForm) -> String : "High Form Check"
 public defmethod short-name (b:CheckHighForm) -> String : "high-form-check"
 
@@ -94,6 +97,22 @@ defn WrongReset (info:FileInfo, name:Symbol) :
    PassException $ string-join $
    [info ": Module " name " has a reset that is not of type UInt<1>."]
 
+defn IncorrectNumArgs (info:FileInfo, op:Symbol, n:Int) :
+   PassException $ string-join $
+   [info ": Primop " op " requires " n " expression arguments."]
+
+defn IncorrectNumConsts (info:FileInfo, op:Symbol, n:Int) :
+   PassException $ string-join $
+   [info ": Primop " op " requires " n " integer arguments."]
+
+defn NegWidth (info:FileInfo) :
+   PassException $ string-join $
+   [info ": Width cannot be negative."]
+
+defn NegVecSize (info:FileInfo) :
+   PassException $ string-join $
+   [info ": Vector type size cannot be negative."]
+
 ;---------------- Helper Functions --------------
 defn has-flip? (t:Type) -> True|False :
    var has? = false
@@ -114,28 +133,70 @@ defn contains?<?T> (c:?T,cs:Streamable<?T>) -> True|False :
          if x == c : myret(true)
       false
 
-defn is-prefix? (s:Symbol,v:Vector<Symbol>) -> Symbol|False :
+defn is-prefix? (s:Symbol,v:Vector<Symbol>,sym:Symbol) -> Symbol|False :
+   defn is-prefix? (s1:Symbol,s2:Symbol) -> True|False :
+      var is? = true
+      val s1* = to-string(s1)
+      val s2* = to-string(s2)
+      for (x in s1*, y in s2*) do :
+         if x != y : is? = false
+      if length(s1*) > length(s2*) :
+         if s1*[length(s2*)] != to-string(sym)[0] : is? = false
+      if length(s1*) < length(s2*) :
+         if s2*[length(s1*)] != to-string(sym)[0] : is? = false
+      if length(s1*) == length(s2*) :
+         is? = false
+      is?
    label<Symbol|False> myret :
       for x in v do :
          if is-prefix?(x,s) : myret(x)
       false
 
-defn is-prefix? (s1:Symbol,s2:Symbol) -> True|False :
-   var is? = true
-   val s1* = to-string(s1)
-   val s2* = to-string(s2)
-   for (x in s1*, y in s2*) do :
-      if x != y : is? = false
-   if length(s1*) > length(s2*) :
-      if s1*[length(s2*)] != '$' : is? = false
-   if length(s1*) < length(s2*) :
-      if s2*[length(s1*)] != '$' : is? = false
-   if length(s1*) == length(s2*) :
-      is? = false
-   is?
+defn check-high-form-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) -> False :
+   defn correct-num (ne:Int|False,nc:Int) -> False :
+      if not (ne typeof False) : 
+         if length(args(e)) != ne as Int : add(errors,IncorrectNumArgs(info,to-symbol(op(e)),ne as Int))
+      if length(consts(e)) != nc : add(errors,IncorrectNumConsts(info,to-symbol $ op(e),nc))
+
+   switch {op(e) == _} :
+      ADD-OP             : correct-num(2,0)
+      SUB-OP             : correct-num(2,0)
+      MUL-OP             : correct-num(2,0)
+      DIV-OP             : correct-num(2,0)
+      MOD-OP             : correct-num(2,0)
+      QUO-OP             : correct-num(2,0)
+      REM-OP             : correct-num(2,0)
+      ADD-WRAP-OP        : correct-num(2,0)
+      SUB-WRAP-OP        : correct-num(2,0)
+      LESS-OP            : correct-num(2,0)
+      LESS-EQ-OP         : correct-num(2,0)
+      GREATER-OP         : correct-num(2,0)
+      GREATER-EQ-OP      : correct-num(2,0)
+      EQUAL-OP           : correct-num(2,0)
+      NEQUAL-OP          : correct-num(2,0)
+      MUX-OP             : correct-num(3,0)
+      PAD-OP             : correct-num(1,1)
+      AS-UINT-OP         : correct-num(1,0)
+      AS-SINT-OP         : correct-num(1,0)
+      DYN-SHIFT-LEFT-OP  : correct-num(2,0)
+      DYN-SHIFT-RIGHT-OP : correct-num(2,0)
+      SHIFT-LEFT-OP      : correct-num(1,1)
+      SHIFT-RIGHT-OP     : correct-num(1,1)
+      CONVERT-OP         : correct-num(1,0)
+      NEG-OP             : correct-num(1,0)
+      BIT-NOT-OP         : correct-num(1,0)
+      BIT-AND-OP         : correct-num(2,0)
+      BIT-OR-OP          : correct-num(2,0)
+      BIT-XOR-OP         : correct-num(2,0)
+      BIT-AND-REDUCE-OP  : correct-num(false,0)
+      BIT-OR-REDUCE-OP   : correct-num(false,0)
+      BIT-XOR-REDUCE-OP  : correct-num(false,0)
+      CONCAT-OP          : correct-num(2,0)
+      BIT-SELECT-OP      : correct-num(1,1)
+      BITS-SELECT-OP     : correct-num(1,2)
 
 ;--------------- Check High Form Pass -------------------
-public defn check-high-form (c:Circuit) -> Circuit : 
+public defn check-high-form (c:Circuit,sym:Symbol) -> Circuit : 
    val errors = Vector<PassException>()
 
    defn check-valid-loc (info:FileInfo,e:Expression) -> False :
@@ -144,6 +205,20 @@ public defn check-high-form (c:Circuit) -> Circuit :
             add(errors,InvalidLOC(info))
          (e) : false
 
+   defn check-high-form-w (info:FileInfo,w:Width) -> Width :
+      match(w) :
+         (w:IntWidth) : 
+            if width(w) < 0 : add(errors,NegWidth(info))
+            w
+         (w) : w
+
+   defn check-high-form-t (info:FileInfo,t:Type) -> Type :
+      match(map(check-high-form-t{info,_},t)) :
+         (t:VectorType) : 
+            if size(t) < 0 : add(errors,NegVecSize(info))
+         (t) : false
+      map(check-high-form-w{info,_:Width},t)
+      
    defn check-high-form-e (info:FileInfo,e:Expression,names:Vector<Symbol>) -> Expression :
       match(map(check-high-form-e{info,_,names},e)) :
          (e:Ref) : 
@@ -157,18 +232,23 @@ public defn check-high-form (c:Circuit) -> Circuit :
             match(exp(e)) :
                (e:Ref|Subfield|Index) : false
                (e) : add(errors,InvalidIndex(info))
+         (e:DoPrim) : check-high-form-primop(e,errors,info)
          ;; (e:UIntValue) :
          ;; if value(e) < 0 : 
          ;;    add(errors,NegUInt(info))
          (e) : false
+      map(check-high-form-w{info,_:Width},e)
+      map(check-high-form-t{info,_:Type},e)
       e
 
    defn check-high-form-s (s:Stmt,names:Vector<Symbol>) -> Stmt :
       defn check-name (info:FileInfo,name:Symbol) -> False :
          if contains?(name,names) : add(errors,NotUnique(info,name))
-         val prefix = is-prefix?(name,names)
+         val prefix = is-prefix?(name,names,sym)
          if prefix typeof Symbol : add(errors,IsPrefix(info,name,prefix as Symbol))
 
+      map(check-high-form-t{info(s),_:Type},s)
+
       map{check-high-form-s{_,names},_} $ { 
          match(map(check-high-form-e{info(s),_,names},s)) :
             (s:DefWire|DefRegister) :
@@ -191,6 +271,8 @@ public defn check-high-form (c:Circuit) -> Circuit :
                add(names,name(s))
             (s:Connect) : 
                check-valid-loc(info(s),loc(s))
+            (s:BulkConnect) : 
+               check-valid-loc(info(s),loc(s))
             (s) : false
          s }()
 
@@ -209,10 +291,15 @@ public defn check-high-form (c:Circuit) -> Circuit :
                      add(errors,WrongReset(info!(m),name(m)))
                else :
                   add(errors,WrongReset(info!(m),name(m)))
+         map(check-high-form-t{info(p),_},type(p))
+         map(check-high-form-w{info(p),_},type(p))
+
 
       
       add(names,`reset)
-      check-high-form-s(body(m),names)
+      match(m) :
+         (m:ExModule) : false
+         (m:InModule) : check-high-form-s(body(m),names)
       false
    
    var number-top-m = 0
@@ -284,8 +371,6 @@ public defn check-kinds (c:Circuit) -> Circuit :
             check-is-mem(info,mem(e))
             check-not-mem(info,index(e))
             check-not-mem(info,enable(e))
-         ;(e:Pad) :
-            ;check-not-mem(info,value(e))
          (e) : do(check-not-mem{info,_},e)
    defn check-kinds-s (s:Stmt) -> False :
       do(check-kinds-e{info(s),_:Expression},s)
@@ -296,6 +381,9 @@ public defn check-kinds (c:Circuit) -> Circuit :
          (s:Connect) : 
             check-not-mem(info(s),loc(s))
             check-not-mem(info(s),exp(s))
+         (s:BulkConnect) : 
+            check-not-mem(info(s),loc(s))
+            check-not-mem(info(s),exp(s))
          (s:OnReset) : 
             check-is-reg(info(s),loc(s))
             check-not-mem(info(s),exp(s))
@@ -303,13 +391,14 @@ public defn check-kinds (c:Circuit) -> Circuit :
       do(check-kinds-s,s)
    
    for m in modules(c) do :
-      check-kinds-s(body(m))
+      match(m) :
+         (m:ExModule) : false
+         (m:InModule) : check-kinds-s(body(m))
    throw(PassExceptions(errors)) when not empty?(errors)
    c
 
 
 ;==================== CHECK TYPES =====================
-; o expression in pad must be a ground type
 ; o Subfields are only on bundles, before type inference <- need to not error, just do unknown-type
 ; o Indexes are only on vectors
 ; o pred in conditionally must be of type UInt
@@ -348,10 +437,6 @@ defn EnableNotUInt (info:FileInfo) :
    PassException $ string-join $
    [info ": Enable is not of UIntType."]
 
-;defn PadNotGround (info:FileInfo) :
-   ;PassException $ string-join $
-   ;[info ": Illegal Pad on non-ground type."]
-
 defn InvalidConnect (info:FileInfo) :
    PassException $ string-join $
    [info ": Type mismatch."]
@@ -360,6 +445,27 @@ defn PredNotUInt (info:FileInfo) :
    PassException $ string-join $
    [info ": Predicate not a UIntType."]
 
+defn OpNotGround (info:FileInfo, op:Symbol) :
+   PassException $ string-join $
+   [info ": Primop " op " cannot operate on non-ground types."]
+
+defn OpNotUInt (info:FileInfo, op:Symbol,e:Symbol) :
+   PassException $ string-join $
+   [info ": Primop " op " requires argument " e " to be a UInt type."]
+
+defn OpNotAllUInt (info:FileInfo, op:Symbol) :
+   PassException $ string-join $
+   [info ": Primop " op " requires all arguments to be UInt type."]
+
+defn OpNotAllSameType (info:FileInfo, op:Symbol) :
+   PassException $ string-join $
+   [info ": Primop " op " requires all operands to have the same type."]
+
+defn NodeWithFlips (info:FileInfo) :
+   PassException $ string-join $
+   [info ": Node cannot be a bundle type with flips."]
+
+
 ;---------------- Helper Functions --------------
 defmethod equal? (t1:Type,t2:Type) -> True|False :
    match(t1,t2) : 
@@ -380,6 +486,64 @@ defmethod equal? (t1:Type,t2:Type) -> True|False :
 defn u () -> UIntType : UIntType(UnknownWidth())
 defn s () -> SIntType : SIntType(UnknownWidth())
 
+defn check-types-primop (e:DoPrim, errors:Vector<PassException>,info:FileInfo) -> False :
+   defn all-same-type (ls:List<Expression>) -> False :
+      for x in ls do :
+         if type(head(ls)) != type(x) : 
+           add(errors,OpNotAllSameType(info,to-symbol $ op(e))) 
+   defn all-ground (ls:List<Expression>) -> False :
+      for x in ls do :
+         if not (type(x) typeof UIntType or type(x) typeof SIntType) :
+           add(errors,OpNotGround(info,to-symbol $ op(e))) 
+   defn all-uint (ls:List<Expression>) -> False :
+      for x in ls do :
+         if not (type(x) typeof UIntType) : 
+           add(errors,OpNotAllUInt(info,to-symbol $ op(e))) 
+   defn is-uint (x:Expression) -> False : 
+      if not (type(x) typeof UIntType) : 
+        add(errors,OpNotUInt(info,to-symbol $ op(e),to-symbol(x))) 
+   
+   all-ground(args(e))
+
+   switch {op(e) == _} :
+      ADD-OP             : false
+      SUB-OP             : false
+      MUL-OP             : false
+      DIV-OP             : false
+      MOD-OP             : false
+      QUO-OP             : false
+      REM-OP             : false
+      ADD-WRAP-OP        : false
+      SUB-WRAP-OP        : false
+      LESS-OP            : false
+      LESS-EQ-OP         : false
+      GREATER-OP         : false
+      GREATER-EQ-OP      : false
+      EQUAL-OP           : all-same-type(args(e))
+      NEQUAL-OP          : all-same-type(args(e))
+      MUX-OP             : 
+         all-same-type(tail(args(e)))
+         is-uint(head(args(e)))
+      PAD-OP             : false
+      AS-UINT-OP         : false
+      AS-SINT-OP         : false
+      DYN-SHIFT-LEFT-OP  : is-uint(args(e)[1])
+      DYN-SHIFT-RIGHT-OP : is-uint(args(e)[1])
+      SHIFT-LEFT-OP      : false
+      SHIFT-RIGHT-OP     : false
+      CONVERT-OP         : false
+      NEG-OP             : false
+      BIT-NOT-OP         : all-uint(args(e))
+      BIT-AND-OP         : all-uint(args(e))
+      BIT-OR-OP          : all-uint(args(e))
+      BIT-XOR-OP         : all-uint(args(e))
+      BIT-AND-REDUCE-OP  : all-uint(args(e))
+      BIT-OR-REDUCE-OP   : all-uint(args(e))
+      BIT-XOR-REDUCE-OP  : all-uint(args(e))
+      CONCAT-OP          : all-uint(args(e))
+      BIT-SELECT-OP      : all-uint(args(e))
+      BITS-SELECT-OP     : all-uint(args(e))
+   
 ;----------------- Check Types Pass ---------------------
 public defn check-types (c:Circuit) -> Circuit : 
    val errors = Vector<PassException>()
@@ -397,33 +561,32 @@ public defn check-types (c:Circuit) -> Circuit :
                (t:VectorType) : 
                   if value(e) >= size(t) : add(errors,IndexTooLarge(info,value(e)))
                (t) : add(errors,IndexOnNonVector(info))
-         (e:DoPrim) : false ;check-types-primop(e)
+         (e:DoPrim) : check-types-primop(e,errors,info)
          (e:ReadPort|WritePort) : 
             if type(index(e)) != u() : add(errors,IndexNotUInt(info))
             if type(enable(e)) != u() : add(errors,EnableNotUInt(info))
          (e:Register) :
             if type(enable(e)) != u() : add(errors,EnableNotUInt(info))
-         ;(e:Pad) :
-            ;val t = type(value(e))
-            ;if not (t == u() or t == s()) : add(errors,PadNotGround(info))
          (e:UIntValue|SIntValue) : false
       e
    defn check-types-s (s:Stmt) -> Stmt :
-      map{check-types-s,_} $ 
-      match(map(check-types-e{info(s),_},s)) : 
-         (s:Connect) : 
-            if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
-            s
-         (s:OnReset) : 
-            if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
-            s
-         (s:Conditionally) :
-            if type(pred(s)) != u() : add(errors,PredNotUInt(info(s)))
-            s
-         (s) : s
+      map{check-types-s,_} $ {
+         match(map(check-types-e{info(s),_},s)) : 
+            (s:Connect) : 
+               if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
+            (s:OnReset) : 
+               if type(loc(s)) != type(exp(s)) : add(errors,InvalidConnect(info(s)))
+            (s:Conditionally) :
+               if type(pred(s)) != u() : add(errors,PredNotUInt(info(s)))
+            (s:DefNode) :
+               if has-flip?(type(value(s))) : add(errors,NodeWithFlips(info(s)))
+            (s) : false
+         s }()
    
    for m in modules(c) do :
-      check-types-s(body(m))
+      match(m) :
+         (m:ExModule) : false
+         (m:InModule) : check-types-s(body(m))
    throw(PassExceptions(errors)) when not empty?(errors)
    c
 
@@ -469,7 +632,6 @@ public defn check-genders (c:Circuit) -> Circuit :
             val f = {_ as Field} $ for f in fields(type(exp(e)) as BundleType) find : name(f) == name(e)
             get-gender(exp(e),genders) * flip(f)
          (e:WIndex) : get-gender(exp(e),genders)
-         ;(e:Pad) : MALE
          (e:DoPrim) : MALE
          (e:UIntValue) : MALE
          (e:SIntValue) : MALE
@@ -483,7 +645,6 @@ public defn check-genders (c:Circuit) -> Circuit :
          (e:WRef) : false
          (e:WSubfield) : false
          (e:WIndex) : false
-         ;(e:Pad) : check-gender(info,genders,value(e),MALE)
          (e:DoPrim) : 
             for e in args(e) do :
                check-gender(info,genders,e,MALE)
@@ -511,6 +672,9 @@ public defn check-genders (c:Circuit) -> Circuit :
          (s:Connect) : 
             check-gender(info(s),genders,loc(s),FEMALE)
             check-gender(info(s),genders,exp(s),MALE)
+         (s:BulkConnect) : 
+            check-gender(info(s),genders,loc(s),FEMALE)
+            check-gender(info(s),genders,exp(s),MALE)
          (s:OnReset) : 
             check-gender(info(s),genders,loc(s),FEMALE)
             check-gender(info(s),genders,exp(s),MALE)
@@ -524,6 +688,9 @@ public defn check-genders (c:Circuit) -> Circuit :
       val genders = HashTable<Symbol,Gender>(symbol-hash)
       for p in ports(m) do :
          genders[name(p)] = dir-to-gender(direction(p))
-      check-genders-s(body(m),genders)
+      match(m) :
+         (m:ExModule) : false
+         (m:InModule) : check-genders-s(body(m),genders)
    throw(PassExceptions(errors)) when not empty?(errors)
    c
+
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 39538498..18e069b4 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -5,6 +5,9 @@ defpackage firrtl/ir2 :
 public defmulti info! (x:?) -> FileInfo
 public defmethod info! (x:?) : FileInfo()
 
+public val expand-delin = `$
+public val gen-delin = `#
+
 public definterface Direction
 public val INPUT = new Direction
 public val OUTPUT = new Direction
@@ -114,6 +117,7 @@ public defstruct DefMemory <: Stmt : ;LOW
    info: FileInfo with: (as-method => true)
    name: Symbol
    type: VectorType
+   seq?: True|False
 public defstruct DefNode <: Stmt : ;LOW
    info: FileInfo with: (as-method => true)
    name: Symbol
@@ -130,7 +134,11 @@ public defstruct Conditionally <: Stmt :
    alt: Stmt
 public defstruct Begin <: Stmt : ;LOW
    body: List<Stmt>
-public defstruct OnReset <: Stmt : ;LOW
+public defstruct OnReset <: Stmt : 
+   info: FileInfo with: (as-method => true)
+   loc: Expression
+   exp: Expression
+public defstruct BulkConnect <: Stmt : 
    info: FileInfo with: (as-method => true)
    loc: Expression
    exp: Expression
@@ -163,12 +171,21 @@ public defstruct Port :
    direction: Direction
    type: Type
 
-public defstruct Module :
+public definterface Module
+public defmulti name (m:Module) -> Symbol
+public defmulti ports (m:Module) -> List<Port>
+
+public defstruct InModule <: Module :
    info: FileInfo
-   name: Symbol
-   ports: List<Port>
+   name: Symbol with: (as-method => true)
+   ports: List<Port> with: (as-method => true)
    body: Stmt
 
+public defstruct ExModule <: Module :
+   info: FileInfo
+   name: Symbol with: (as-method => true)
+   ports: List<Port> with: (as-method => true)
+
 public defstruct Circuit :
    info: FileInfo
    modules: List<Module>
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 5a7e593d..071717bb 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -13,6 +13,10 @@
 #include("flo.stanza")
 #include("verilog.stanza")
 
+;Custom Packages
+#include("custom-passes.stanza")
+#include("custom-compiler.stanza")
+
 defpackage firrtl-main :
    import core
    import verse
@@ -22,6 +26,9 @@ defpackage firrtl-main :
    import stz/parser
    import firrtl/ir-utils
    import firrtl/compiler
+   ;Custom Packages
+   import firrtl/custom-passes
+   import firrtl/custom-compiler
 
 defn set-printvars! (p:List<Char>) :
    if contains(p,'t') : PRINT-TYPES = true
@@ -47,6 +54,7 @@ defn main () :
    var output = false
    var compiler = false
    val pass-names = Vector<String>()
+   val pass-args = Vector<String>()
    var printvars = ""
    for (s in args, i in 0 to false) do :
       if s == "-i" : input = args[i + 1]
@@ -54,6 +62,7 @@ defn main () :
       if s == "-x" : add(pass-names,args[i + 1])
       if s == "-X" : compiler = args[i + 1]
       if s == "-p" : printvars = args[i + 1]
+      if s == "-s" : add(pass-args,args[i + 1])
 
    if input == false : 
       error("No input file provided. Use -i flag.")
@@ -72,6 +81,7 @@ defn main () :
       switch {_ == compiler} :
          "flo" : run-passes(c,StandardFlo(output as String))
          "verilog" : run-passes(c,StandardVerilog(output as String))
+         "verilute" : run-passes(c,InstrumentedVerilog(output as String,to-list $ pass-args))
          else : error("Invalid compiler flag")
 
 main()
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index c75071cd..bb9365ae 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -24,9 +24,11 @@ defn set-width (desired:Int,t:Type) -> Type :
 
 defn pad-widths-e (desired:Int,e:Expression) -> Expression :
    defn trim (desired:Int, e:Expression) :
-     DoPrim(BITS-SELECT-OP,list(e),list(0,desired),set-width(desired,type(e)))
+     ;; println-all(["TRIM " desired " e " e])
+     DoPrim(BITS-SELECT-OP,list(e),list(desired - 1, 0),set-width(desired,type(e)))
    defn pad (desired:Int, e:Expression) :
-     DoPrim(PAD-OP,list(e),list(),set-width(desired,type(e)))
+     ;; println-all(["PAD " desired " e " e])
+     DoPrim(PAD-OP,list(e),list(desired),set-width(desired,type(e)))
    defn trim-pad (desired:Int, e:Expression) :
      val i = int-width!(type(e))
      if i > desired : trim(desired, e)
@@ -83,7 +85,9 @@ defn pad-widths-s (s:Stmt) -> Stmt :
 public defn pad-widths (c:Circuit) -> Circuit :
    Circuit{info(c),_,main(c)} $
       for m in modules(c) map :
-         Module(info(m),name(m),ports(m),pad-widths-s(body(m)))
+         match(m) :
+            (m:ExModule) : error("Cannot use flo backend with external modules")
+            (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m)))
 
 ;============= Flo Backend ================
 
@@ -217,7 +221,7 @@ defn maybe-mov (e:Expression) -> String :
       (e) :           false
    if need-mov?: "mov " else: ""
 
-defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol) :
+defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol,sh:HashTable<Symbol,Int>) :
    match(s) :
       (s:DefWire) : ""
       (s:DefInstance) : error("Shouldn't be here")
@@ -226,7 +230,7 @@ defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol) :
          emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top)
       (s:DefNode) :
          emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top)
-      (s:Begin) : do(emit-s{_, v, top}, body(s))
+      (s:Begin) : do(emit-s{_, v, top,sh}, body(s))
       (s:Connect) : 
          match(loc(s)) :
            (r:Ref) :
@@ -236,14 +240,14 @@ defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol) :
              else :
                 emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top)
            (w:WritePort) :
-             val n = firrtl-gensym(`F)
+             val n = firrtl-gensym(`F,sh)
              emit-all([top "::" n " = wr'" prim-width(type(w)) " " enable(w) " " mem(w) " " index(w) " " exp(s) "\n"], top)
            (o) :
              println-all(["CONNEcT LOC " loc(s)])
              error("Unknown Connect")
       (s) : s 
 
-defn emit-module (m:Module) :
+defn emit-module (m:InModule,sh:HashTable<Symbol,Int>) :
    val v = Vector<Symbol>()
    for port in ports(m) do :
       if name(port) ==`reset :
@@ -251,10 +255,10 @@ defn emit-module (m:Module) :
       else : switch {_ == direction(port)} :
          INPUT : print-all([name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"])
          OUTPUT : add(v,name(port))
-   emit-s(body(m), to-list(v), name(m))
+   emit-s(body(m), to-list(v), name(m),sh)
 
 public defn emit-flo (file:String, c:Circuit) :
    with-output-file{file, _} $ fn () :
-      emit-module(modules(c)[0])
+      emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule))
       false
    c
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 0833543f..cbfe106e 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -151,9 +151,15 @@ defsyntax firrtl :
       module = (module ?name:#id! #:! (?ps:#port ... ?cs:#stmt ... ?rest ...)) :
          if not empty?(rest) :
             FPE(rest, "Expected a statement here.")
-         Module(first-info(form),name, ps, Begin(cs))
+         InModule(first-info(form),name, ps, Begin(cs))
+      module = (exmodule ?name:#id! #:! (?ps:#port ... ?rest ...)) :
+         if not empty?(rest) :
+            FPE(rest, "Expected a port here.")
+         ExModule(first-info(form),name, ps)
       module != (module) :
          FPE(form, "Invalid syntax for module definition.")
+      module != (exmodule) :
+         FPE(form, "Invalid syntax for exmodule definition.")
    
    defrule port :
       port = (input ?name:#id! #:! ?type:#type!) : Port(first-info(form),name, INPUT, type)
@@ -187,13 +193,15 @@ defsyntax firrtl :
    defrule statements :
       stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t)
       stmt = (reg ?name:#id! #:! ?t:#type!) : DefRegister(first-info(form),name, t)
-      stmt = (mem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t)
+      stmt = (cmem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, false)
+      stmt = (smem ?name:#id! #:! ?t:#vectype!) : DefMemory(first-info(form),name, t, true)
       stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name, m)
       stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name, e)
       stmt = (accessor ?name:#id! #=! ?s:#exp![?i:#exp$]) : DefAccessor(first-info(form),name, s, i)
       stmt = (?s:#stmt/when) : s
 
       stmt = (?x:#exp := ?y:#exp!) : Connect(first-info(form),x, y)
+      stmt = (?x:#exp <> ?y:#exp!) : BulkConnect(first-info(form),x, y)
       stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(first-info(form),x, y)
 
       stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index d2afca05..c39a1ad1 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -9,15 +9,42 @@ public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|M
 
 ;============== GENSYM STUFF ======================
 
-val sym-hash = HashTable<Symbol,Int>(symbol-hash)
-public defn firrtl-gensym (s:Symbol) -> Symbol :
-   val cur = get?(sym-hash,s,0)
-   val nxt = cur + 1
-   sym-hash[s] = nxt
-   symbol-join([s cur])
+
+public defn firrtl-gensym (s:Symbol) -> Symbol : firrtl-gensym(s,HashTable<Symbol,Int>(symbol-hash))
+
+public defn firrtl-gensym (s:Symbol,sym-hash:HashTable<Symbol,Int>) -> Symbol :
+   defn get-new (s:Symbol, i:Int) -> Symbol :
+      val s* = symbol-join([s i])
+      if contains?(keys(sym-hash),s*) :
+         get-new(s,i + 1)
+      else :
+         sym-hash[s] = i
+         sym-hash[s*] = 0
+         s*
+   get-new(s,0)
    
-public defn firrtl-gensym () -> Symbol :
-   firrtl-gensym(`gen)
+public defn firrtl-gensym (sym-hash:HashTable<Symbol,Int>) -> Symbol :
+   firrtl-gensym(`gen,sym-hash)
+
+public defn get-sym-hash (m:InModule) -> HashTable<Symbol,Int> :
+   val sym-hash = HashTable<Symbol,Int>(symbol-hash)
+   defn add-name (s:Symbol) -> False :
+      sym-hash[s] = 0
+   defn to-port (p:Port) -> False : add-name(name(p))
+   defn to-stmt (s:Stmt) -> Stmt :
+     match(s) :
+        (s:DefWire) : add-name(name(s))
+        (s:DefRegister) : add-name(name(s))
+        (s:DefInstance) : add-name(name(s))
+        (s:DefMemory) : add-name(name(s))
+        (s:DefNode) : add-name(name(s))
+        (s:DefAccessor) : add-name(name(s))
+        (s) : false
+     map(to-stmt,s)
+
+   to-stmt(body(m))
+   map(to-port,ports(m))
+   sym-hash
    
 ;============== Exceptions =====================
 
@@ -127,7 +154,8 @@ defmethod print (o:OutputStream, c:Stmt) :
       (c:DefRegister) : 
          print-all(o,["reg " name(c) " : " type(c)])
       (c:DefMemory) :
-         print-all(o,["mem " name(c) " : " type(c)])
+         if seq?(c) : print-all(o,["smem " name(c) " : " type(c)])
+         else       : print-all(o,["cmem " name(c) " : " type(c)])
       (c:DefInstance) :
          print-all(o,["inst " name(c) " of " module(c)])
       (c:DefNode) :
@@ -147,6 +175,8 @@ defmethod print (o:OutputStream, c:Stmt) :
          do(print{o,_}, join(body(c), "\n"))
       (c:Connect) :
          print-all(o, [loc(c) " := " exp(c)])
+      (c:BulkConnect) :
+         print-all(o, [loc(c) " <> " exp(c)])
       (c:OnReset) :
          print-all(o, ["on-reset " loc(c) " := " exp(c)])
       (c:EmptyStmt) :
@@ -181,7 +211,7 @@ defmethod print (o:OutputStream, p:Port) :
    print-all(o, [direction(p) " " name(p) " : " type(p)])
    print-debug(o,p)
 
-defmethod print (o:OutputStream, m:Module) :
+defmethod print (o:OutputStream, m:InModule) :
    print-all(o, ["module " name(m) " :"])
    print-debug(o,m)
    print(o,"\n")
@@ -190,6 +220,14 @@ defmethod print (o:OutputStream, m:Module) :
       println(io,p)
    print(io,body(m))
 
+defmethod print (o:OutputStream, m:ExModule) :
+   print-all(o, ["exmodule " name(m) " :"])
+   print-debug(o,m)
+   print(o,"\n")
+   val io = IndentedStream(o, 3)
+   for p in ports(m) do :
+      println(io,p)
+
 defmethod print (o:OutputStream, c:Circuit) :
    print-all(o, ["circuit " main(c) " :"])
    print-debug(o,c)
@@ -231,6 +269,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
       (c:DefInstance) : DefInstance(info(c),name(c), f(module(c)))
       (c:Conditionally) : Conditionally(info(c),f(pred(c)), conseq(c), alt(c))
       (c:Connect) : Connect(info(c),f(loc(c)), f(exp(c)))
+      (c:BulkConnect) : BulkConnect(info(c),f(loc(c)), f(exp(c)))
       (c:OnReset) : OnReset(info(c),f(loc(c)),f(exp(c)))
       (c) : c
 
@@ -272,7 +311,7 @@ defmethod map (f: Type -> Type, c:Stmt) -> Stmt :
    match(c) :
       (c:DefWire) : DefWire(info(c),name(c),f(type(c)))
       (c:DefRegister) : DefRegister(info(c),name(c),f(type(c)))
-      (c:DefMemory) : DefMemory(info(c),name(c),f(type(c)) as VectorType)
+      (c:DefMemory) : DefMemory(info(c),name(c),f(type(c)) as VectorType,seq?(c))
       (c) : c
 
 public defmulti mapr<?T> (f: Width -> Width, t:?T&Type) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index b6926a7b..80035325 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -9,7 +9,7 @@ defpackage firrtl/passes :
 
 ;============== Pass List ================
 public val standard-passes = to-list $ [
-   CheckHighForm()
+   CheckHighForm(expand-delin)
    TempElimination()
    ToWorkingIR()
    MakeExplicitReset()
@@ -85,6 +85,11 @@ defstruct ConnectFromIndexed <: Stmt :
 
 
 ;================ WORKING IR UTILS =========================
+;defmethod equal? (f1:Flip, f2:Flip) -> True|False :
+;   switch fn ([x,y]) : f1 == x and f2 == y :
+;      [DEFAULT,DEFAULT] : true
+;      [REVERSE,REVERSE] : true
+;      else : false
 
 defn plus (g1:Gender,g2:Gender) -> Gender :
    switch fn ([x,y]) : g1 == x and g2 == y :
@@ -304,7 +309,9 @@ defn temp-elimination (c:Circuit) :
    Circuit(info(c),modules*, main(c)) where :
       val modules* =
          for m in modules(c) map :
-            Module(info(m),name(m), ports(m), temp-elim-s(body(m)))
+            match(m) :
+               (m:InModule) : InModule(info(m),name(m), ports(m), temp-elim-s(body(m)))
+               (m:ExModule) : m
 
 ;================= Bring to Working IR ========================
 ; Returns a new Circuit with Refs, Subfields, Indexes and DefAccessors 
@@ -330,7 +337,9 @@ defn to-working-ir (c:Circuit) :
    Circuit(info(c),modules*, main(c)) where :
       val modules* =
          for m in modules(c) map :
-            Module(info(m),name(m), ports(m), to-stmt(body(m)))
+            match(m) :
+               (m:InModule) : InModule(info(m),name(m), ports(m), to-stmt(body(m)))
+               (m:ExModule) : m
 
 ;=============== MAKE EXPLICIT RESET =======================
 ; All modules have an implicit reset signal - however, the 
@@ -367,8 +376,11 @@ defn make-explicit-reset (c:Circuit) :
       var ports! = ports(m)
       if not contains?(explicit-reset,name(m)) :
          ports! = append(ports(m),list(Port(FileInfo(),`reset,INPUT,UIntType(IntWidth(1)))))
-      val body! = route-reset(body(m))
-      Module(info(m),name(m),ports!,body!)
+      match(m) :
+         (m:InModule) : 
+            val body! = route-reset(body(m))
+            InModule(info(m),name(m),ports!,body!)
+         (m:ExModule) : ExModule(info(m),name(m),ports!)
       
    defn make-explicit-reset (m:Module, c:Circuit) -> Module :
       val explicit-reset = find-explicit(c)
@@ -417,15 +429,20 @@ defn resolve-kinds (c:Circuit) :
       kinds[name(m)] = ModuleKind()
       for p in ports(m) do :
          kinds[name(p)] = PortKind()
-      find-stmt(body(m))
+      match(m) : 
+         (m:InModule) : find-stmt(body(m))
+         (m:ExModule) : false
     
    defn resolve-kinds (m:Module, c:Circuit) -> Module :
       val kinds = HashTable<Symbol,Kind>(symbol-hash)
       for m in modules(c) do :
          kinds[name(m)] = ModuleKind()
       find(m,kinds)   
-      val body! = resolve(body(m),kinds)
-      Module(info(m),name(m),ports(m),body!)
+      match(m) : 
+         (m:InModule) : 
+            val body! = resolve(body(m),kinds)
+            InModule(info(m),name(m),ports(m),body!)
+         (m:ExModule) : ExModule(info(m),name(m),ports(m))
 
    Circuit(info(c),modules*, main(c)) where :
       val modules* = 
@@ -504,15 +521,18 @@ defn infer-types (s:Stmt, l:List<KeyValue<Symbol,Type>>) -> [Stmt List<KeyValue<
         val [s*,l*] = infer-types(conseq(s),l)
         val [s**,l**] = infer-types(alt(s),l)
         [Conditionally(info(s),pred(s),s*,s**),l]
-      (s:Connect|OnReset|EmptyStmt) : [s,l]
+      (s:Connect|BulkConnect|OnReset|EmptyStmt) : [s,l]
 
 defn infer-types (m:Module, l:List<KeyValue<Symbol,Type>>) -> Module :
    val ptypes = 
       for p in ports(m) map :
          name(p) => type(p)
    println-all-debug(append(ptypes,l))
-   val [s,l*] = infer-types(body(m),append(ptypes, l))
-   Module(info(m),name(m),ports(m),s)
+   match(m) :
+      (m:InModule) :
+         val [s,l*] = infer-types(body(m),append(ptypes, l))
+         InModule(info(m),name(m),ports(m),s)
+      (m:ExModule) : m
 
 defn infer-types (c:Circuit) -> Circuit :
    val l = 
@@ -565,8 +585,11 @@ defn resolve-genders (c:Circuit) :
       var done? = true
 
       defn resolve-iter (m:Module) -> Module : 
-         val body* = resolve-stmt(body(m))
-         Module(info(m),name(m),ports(m),body*)
+         match(m) :
+            (m:InModule) :
+               val body* = resolve-stmt(body(m))
+               InModule(info(m),name(m),ports(m),body*)
+            (m:ExModule) : m
 
       defn get-gender (n:Symbol,g:Gender) -> Gender :
          defn force-gender (n:Symbol,g:Gender) -> Gender : 
@@ -607,6 +630,8 @@ defn resolve-genders (c:Circuit) :
                WDefAccessor(info(s),name(s),source*,index*,gender*)
             (s:Connect) : 
                Connect(info(s),resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE))
+            (s:BulkConnect) : 
+               BulkConnect(info(s),resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE))
             (s:OnReset) : 
                OnReset(info(s),resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE))
             (s:Conditionally) :
@@ -696,7 +721,9 @@ defn expand-accessors (c:Circuit) :
    Circuit(info(c),modules*, main(c)) where :
       val modules* = 
          for m in modules(c) map :
-            Module(info(m),name(m),ports(m),expand-stmt(body(m)))
+            match(m) :
+               (m:InModule) : InModule(info(m),name(m),ports(m),expand-stmt(body(m)))
+               (m:ExModule) : m
 
 ;;=============== LOWERING TO GROUND TYPES =============================
 ; All non-ground (elevated) types (Vectors, Bundles) are expanded out to
@@ -742,9 +769,8 @@ defn index-of-elem (t:BundleType, s:Symbol) -> Int :
          else : sum = sum + num-elems(type(f))
       error("Shouldn't be here")
 
-
 defn generate-entry (n:Symbol,t:Type) -> List<NTF> :
-   defn uniquify (n*:Symbol) -> Symbol : symbol-join([n "_" n*])
+   defn uniquify (n*:Symbol) -> Symbol : symbol-join([n expand-delin n*])
    match(t) :
       (t:BundleType) : 
          for f in fields(t) map-append :
@@ -840,7 +866,7 @@ defn lower (body:Stmt) -> Stmt :
                DefNode(info(s),name(s),exp(x))
          (s:DefMemory) : Begin $ 
             for x in generate-entry(name(s),type(type(s))) map :
-               DefMemory(info(s),name(x),VectorType(type(x),size(s)))
+               DefMemory(info(s),name(x),VectorType(type(x),size(s)), seq?(s))
          (s:WDefAccessor) : 
             val ls = generate-entry(name(s),type(s))
             val rs = generate-entry(name(source(s) as WRef),type(s))
@@ -863,6 +889,28 @@ defn lower (body:Stmt) -> Stmt :
                   [MALE,FEMALE]  : 
                      if s typeof Connect : Connect(info(s),r*,l*)
                      else : OnReset(info(s),r*,l*)
+         (s:BulkConnect) :
+            val ls-fake = generate-entry(`null,type(loc(s)))
+            val rs-fake = generate-entry(`null,type(exp(s)))
+            val ls = expand-expr(loc(s))
+            val rs = expand-expr(exp(s))
+            val ls* = Vector<EF>()
+            val rs* = Vector<EF>()
+            for (l-fake in ls-fake,l in ls) do :
+               for (r-fake in rs-fake, r in rs) do :
+                  if name(l-fake) == name(r-fake) and flip(l-fake) == flip(r-fake) and type(l-fake) == type(r-fake) :
+                     add(ls*,l)
+                     add(rs*,r)
+            Begin $ for (l in to-list(ls*), r in to-list(rs*)) map :
+               val lgender = FEMALE * flip(l)
+               val rgender = MALE * flip(r)
+               val l* = set-gender(exp(l),lgender,flip(l))
+               val r* = set-gender(exp(r),rgender,flip(r))
+               println-all-debug(["Left: " l " with Gender: " lgender])
+               println-all-debug(["Right: " r " with Gender: " rgender])
+               switch fn ([x,y]) : lgender == x and rgender == y :
+                  [FEMALE,MALE]  : Connect(info(s),l*,r*)
+                  [MALE,FEMALE]  : Connect(info(s),r*,l*)
          (s:ConnectFromIndexed) : Begin(ls) where :
             val ctable = HashTable<Symbol,Vector<EF>>(symbol-hash)
             for e in exps(s) do :
@@ -908,9 +956,13 @@ defn lower (body:Stmt) -> Stmt :
    lower-stmt(body)
 
 defn lower-module (c:Circuit,m:Module) -> Module : 
-   Module(info(m),name(m),ports*,body*) where :
-      val body* = lower(body(m))
-      val ports* = lower-ports(ports(m))
+   val ports* = lower-ports(ports(m))
+   match(m) :
+      (m:InModule) :
+         val body* = lower(body(m))
+         InModule(info(m),name(m),ports*,body*)
+      (m:ExModule) :
+         ExModule(info(m),name(m),ports*)
 
 defn lower-to-ground (c:Circuit) -> Circuit :
    Circuit(info(c),modules*, main(c)) where :
@@ -928,20 +980,20 @@ public defmethod pass (b:ExpandIndexedConnects) -> (Circuit -> Circuit) : expand
 public defmethod name (b:ExpandIndexedConnects) -> String : "Expand Indexed Connects"
 public defmethod short-name (b:ExpandIndexedConnects) -> String : "expand-indexed-connects"
 
-defn expand-connect-indexed-stmt (s: Stmt) -> Stmt :
+defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt :
    defn equality (e1:Expression,e2:Expression) -> Expression :
       DoPrim(EQUAL-OP,list(e1,e2),List(),UIntType(UnknownWidth()))
    defn get-name (e:Expression) -> Symbol :
       match(e) :
-         (e:WRef) : symbol-join([name(e) `__])
-         (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) `__])
-         (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) `__])
+         (e:WRef) : symbol-join([name(e) gen-delin])
+         (e:WSubfield) : symbol-join([get-name(exp(e)) `. name(e) gen-delin])
+         (e:WIndex) : symbol-join([get-name(exp(e)) `. to-symbol(value(e)) gen-delin])
          (e) : `T
    match(s) :
       (s:ConnectToIndexed) : Begin $
          if length(locs(s)) == 0 : list(EmptyStmt())
          else :
-            val ref = WRef(firrtl-gensym(get-name(exp(s))),type(index(s)),NodeKind(),UNKNOWN-GENDER)
+            val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER)
             append(
                list(DefNode(info(s),name(ref),index(s)))
                to-list $
@@ -955,7 +1007,7 @@ defn expand-connect-indexed-stmt (s: Stmt) -> Stmt :
       (s:ConnectFromIndexed) : Begin $
          if length(exps(s)) == 0 : list(EmptyStmt())
          else :
-            val ref = WRef(firrtl-gensym(get-name(loc(s))),type(index(s)),NodeKind(),UNKNOWN-GENDER)
+            val ref = WRef(firrtl-gensym(get-name(index(s)),sh),type(index(s)),NodeKind(),UNKNOWN-GENDER)
             append(
                list(Connect(info(s),loc(s),head(exps(s))),DefNode(info(s),name(ref),index(s)))
                to-list $
@@ -966,10 +1018,14 @@ defn expand-connect-indexed-stmt (s: Stmt) -> Stmt :
                      EmptyStmt()
                   )
             )
-      (s) : map(expand-connect-indexed-stmt,s)
+      (s) : map(expand-connect-indexed-stmt{_,sh},s)
   
 defn expand-connect-indexed (m: Module) -> Module :
-   Module(info(m),name(m),ports(m),expand-connect-indexed-stmt(body(m)))
+   match(m) :
+      (m:InModule) : 
+         val sh = get-sym-hash(m)
+         InModule(info(m),name(m),ports(m),expand-connect-indexed-stmt(body(m),sh))
+      (m:ExModule) : m
 
 defn expand-connect-indexed (c: Circuit) -> Circuit :
   Circuit(info(c),modules*, main(c)) where :
@@ -1173,63 +1229,49 @@ defn expand-whens (ports:List<Port>, table:HashTable<Symbol,SymbolicValue>,cons:
    for p in ports do :
       if direction(p) == OUTPUT :
          val ref = WRef(name(p),type(p),PortKind(),FEMALE)
-         add{cons,_} $ 
-            if has-nul?(table[name(p)]) : 
-               println("Uninitialized: ~" % [to-string(name(p))]);TODO actually collect error
-               EmptyStmt()
-            else : Connect(FileInfo(),ref,to-exp(table[name(p)]) as Expression)
+         if has-nul?(table[name(p)]) : 
+            println("Uninitialized: ~" % [to-string(name(p))]);TODO actually collect error
+         else : add{cons,_} $ Connect(FileInfo(),ref,to-exp(table[name(p)]) as Expression)
 
 defn expand-whens (s:Stmt, table:HashTable<Symbol,SymbolicValue>,decs:Vector<Stmt>,cons:Vector<Stmt>) -> Stmt :
    match(map(expand-whens{_,table,decs,cons},s)) : 
       (s:DefNode|DefMemory) : add(decs,s)
       (s:DefWire) : 
          add(decs,s)
-         add{cons,_} $ { 
-            val ref = WRef(name(s),type(s),NodeKind(),FEMALE)
-            if has-nul?(table[name(s)]) : 
-               println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error
-               EmptyStmt()
-            else : Connect(info(s),ref,to-exp(table[name(s)]) as Expression)
-            }()
+         val ref = WRef(name(s),type(s),NodeKind(),FEMALE)
+         if has-nul?(table[name(s)]) : 
+            println("Uninitialized: ~" % [to-string(name(s))]);TODO actually collect error
+         else : add{cons,_} $ Connect(info(s),ref,to-exp(table[name(s)]) as Expression)
       (s:DefRegister) : 
-         ;add(decs,DefWire(info(s),name(s),type(s)))
-         ;add{cons,_} $ { 
-         ;   val ref = WRef(name(s),type(s),RegKind(),FEMALE)
-         ;   val e = to-exp(table[name(s)])
-         ;   match(e) : 
-         ;      (e:False) : EmptyStmt()
-         ;      (e:Expression) : Connect(info(s),ref,Register(type(s),e, to-exp(optimize $ get-write-enable(table[name(s)])) as Expression))
-         ;}()
          val e = to-exp(table[name(s)])
-         add{cons,_} $ { 
-            match(e) : 
-               (e:False) : EmptyStmt()
-               (e:Expression) : DefNode(info(s),name(s),Register(type(s),e,to-exp(optimize $ get-write-enable(table[name(s)])) as Expression))
-         }()
+         match(e) : 
+            (e:Expression) : 
+               add{decs,_} $ DefWire(info(s),name(s),type(s))
+               val ref = WRef(name(s),type(s),NodeKind(),FEMALE)
+               add{cons,_} $ Connect(info(s),ref,Register(type(s),e,to-exp(optimize $ get-write-enable(table[name(s)])) as Expression))
+            (e:False) : false
       (s:WDefAccessor) : 
          val t = type(type(source(s)) as VectorType)
          val n = name(s)
-         add{cons,_} $ { 
             switch {_ == gender(s)} :
                MALE : 
-                  Begin $ list $ DefNode(info(s),n,ReadPort(source(s),index(s),t,get-read-enable(n,table)))
+                  add{decs,_} $ DefWire(info(s),n,t)
+                  val ref = WRef(n,t,WriteAccessorKind(),FEMALE)
+                  add{cons,_} $ Connect(info(s),ref,ReadPort(source(s),index(s),t,get-read-enable(n,table)))
                FEMALE :
                   add(decs,DefWire(info(s),n,t))
-                  val ref = WRef(n,t,WriteAccessorKind(),FEMALE)
+                  val ref = WRef(n,t,WriteAccessorKind(),MALE)
+                  val enable = (to-exp $ optimize $ get-write-enable(table[n])) as Expression
+                  val wp = WritePort(source(s),index(s),t,enable as Expression)
                   val e = to-exp(table[n])
-                  val s* = match(e) :
+                  add{cons,_} $ Connect(info(s),wp,ref)
+                  match(e) :
                      (e:False) : 
                         println("Uninitialized: ~" % [to-string(n)]) ;TODO actually collect error
-                        EmptyStmt()
                      (e:Expression) : 
-                        Connect(info(s),ref,e)
-                  val enable = (to-exp $ optimize $ get-write-enable(table[n])) as Expression
-                  val wp = WritePort(source(s),index(s),t,enable as Expression)
-                  Begin $ list(Connect(info(s),wp,ref),s*)
-         }()
+                        add{cons,_} $ Connect(info(s),ref,e)
       (s:DefInstance) : 
          add(decs,s)
-         add{cons,_} $ Begin $ 
             for f in fields(type(module(s)) as BundleType) map :
                if flip(f) == REVERSE : 
                   val n = to-symbol("~.~" % [name(s),name(f)]) ; only on inputs
@@ -1239,9 +1281,7 @@ defn expand-whens (s:Stmt, table:HashTable<Symbol,SymbolicValue>,decs:Vector<Stm
                   val sref = WSubfield(ref,f,bundle-field-type(type(module(s)),f),FEMALE)
                   if has-nul?(table[n]) : 
                      println("Uninitialized: ~" % [to-string(n)]);TODO actually collect error
-                     EmptyStmt()
-                  else : Connect(info(s),sref,to-exp(table[n]) as Expression)
-               else : EmptyStmt()
+                  else : add{cons,_} $ Connect(info(s),sref,to-exp(table[n]) as Expression)
       (s:Connect|Conditionally|OnReset|Begin|EmptyStmt) : false
    s
 
@@ -1347,34 +1387,37 @@ defn build-tables (s:Stmt,
       (s:DefMemory|DefNode|EmptyStmt) : false
          
 defn expand-whens (m:Module) -> Module :
-   val assign = HashTable<Symbol,SymbolicValue>(symbol-hash)
-   val resets = HashTable<Symbol,SymbolicValue>(symbol-hash)
-   val flattn = HashTable<Symbol,True|False>(symbol-hash)
-
-   for p in ports(m) do :
-      if direction(p) == OUTPUT :
-         assign[name(p)] = SVNul()
-         flattn[name(p)] = false
-         
-   build-tables(body(m),assign,resets,flattn)
-   for x in assign do : assign[key(x)] = optimize(value(x))
-   for x in resets do : resets[key(x)] = optimize(value(x))
-   ;val enables = get-enables(assign,kinds)
-   ;for x in enables do : enables[key(x)] = optimize(value(x))
-         
-   println-debug("====== Assigns ======")
-   for x in assign do : println-debug(x)
-   println-debug("====== Resets ======")
-   for x in resets do : println-debug(x)
-
-   val table = merge-resets(assign,resets)
-   println-debug("====== Table ======")
-   for x in table do : println-debug(x)
-   val decs = Vector<Stmt>()
-   val cons = Vector<Stmt>()
-   expand-whens(ports(m),table,cons)
-   expand-whens(body(m),table,decs,cons)
-   Module(info(m),name(m),ports(m),Begin(append(to-list(decs),to-list(cons))))
+   match(m) :
+      (m:ExModule) : m
+      (m:InModule) : 
+         val assign = HashTable<Symbol,SymbolicValue>(symbol-hash)
+         val resets = HashTable<Symbol,SymbolicValue>(symbol-hash)
+         val flattn = HashTable<Symbol,True|False>(symbol-hash)
+
+         for p in ports(m) do :
+            if direction(p) == OUTPUT :
+               assign[name(p)] = SVNul()
+               flattn[name(p)] = false
+               
+         build-tables(body(m),assign,resets,flattn)
+         for x in assign do : assign[key(x)] = optimize(value(x))
+         for x in resets do : resets[key(x)] = optimize(value(x))
+         ;val enables = get-enables(assign,kinds)
+         ;for x in enables do : enables[key(x)] = optimize(value(x))
+               
+         println-debug("====== Assigns ======")
+         for x in assign do : println-debug(x)
+         println-debug("====== Resets ======")
+         for x in resets do : println-debug(x)
+
+         val table = merge-resets(assign,resets)
+         println-debug("====== Table ======")
+         for x in table do : println-debug(x)
+         val decs = Vector<Stmt>()
+         val cons = Vector<Stmt>()
+         expand-whens(ports(m),table,cons)
+         expand-whens(body(m),table,decs,cons)
+         InModule(info(m),name(m),ports(m),Begin(append(to-list(decs),to-list(cons))))
 
 defn expand-whens (c:Circuit) -> Circuit :
    Circuit(info(c),modules*, main(c)) where :
@@ -1409,6 +1452,8 @@ public defstruct MaxWidth <: Width :
 public defstruct ExpWidth <: Width :
    arg1 : Width
 
+val width-name-hash = HashTable<Symbol,Int>(symbol-hash)
+
 public defmulti map<?T> (f: Width -> Width, w:?T&Width) -> T
 defmethod map (f: Width -> Width, w:Width) -> Width :
    match(w) :
@@ -1600,7 +1645,7 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
       match(map(gen-constraints-s,s)) :
          (s:DefWire) : DefWire(info(s),name(s),h[name(s)])
          (s:DefInstance) : DefInstance(info(s),name(s),gen-constraints(module(s)))
-         (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType)
+         (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType,seq?(s))
          (s:DefNode) : 
             val l = h[name(s)]
             val r = gen-constraints(value(s))
@@ -1636,14 +1681,14 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
          (e:UIntValue) : 
             match(width(e)) :
                (w:UnknownWidth) : 
-                  val w* = VarWidth(firrtl-gensym(`w))
+                  val w* = VarWidth(firrtl-gensym(`w,width-name-hash))
                   add(v,WGeq(w*,IntWidth(ceil-log2(value(e)))))
                   UIntValue(value(e),w*)
                (w) : e
          (e:SIntValue) : 
             match(width(e)) :
                (w:UnknownWidth) : 
-                  val w* = VarWidth(firrtl-gensym(`w))
+                  val w* = VarWidth(firrtl-gensym(`w,width-name-hash))
                   add(v,WGeq(w*,IntWidth(1 + ceil-log2(abs(value(e))))))
                   SIntValue(value(e),w*)
                (w) : e
@@ -1652,7 +1697,9 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
    val ports* = 
       for p in ports(m) map : Port(info(p),name(p),direction(p),h[name(p)])
          
-   Module(info(m),name(m),ports*,gen-constraints-s(body(m)))
+   match(m) :
+      (m:ExModule) : ExModule(info(m),name(m),ports*)
+      (m:InModule) : InModule(info(m),name(m),ports*,gen-constraints-s(body(m)))
 
 defn build-environment (c:Circuit,m:Module,h:HashTable<Symbol,Type>) -> HashTable<Symbol,Type> :
    defn build-environment (s:Stmt) -> False :
@@ -1665,7 +1712,10 @@ defn build-environment (c:Circuit,m:Module,h:HashTable<Symbol,Type>) -> HashTabl
       do(build-environment,s)
    for p in ports(m) do :
       h[name(p)] = bundle-field-type(h[name(m)],name(p))
-   build-environment(body(m))
+
+   match(m) :
+      (m:ExModule) : false
+      (m:InModule) : build-environment(body(m))
    h
          
 defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit :
@@ -1706,15 +1756,18 @@ defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit :
       w*
 
    val modules* = for m in modules(c) map :
-      Module{info(m),name(m),_,mapr(reduce-var-widths-w,body(m))} $
-         for p in ports(m) map :
-            Port(info(p),name(p),direction(p),mapr(reduce-var-widths-w,type(p)))
+      val ports* = for p in ports(m) map :
+         Port(info(p),name(p),direction(p),mapr(reduce-var-widths-w,type(p)))
+
+      match(m) :
+         (m:ExModule) : ExModule(info(m),name(m),ports*)
+         (m:InModule) : InModule(info(m),name(m),ports*,mapr(reduce-var-widths-w,body(m)))
 
    Circuit(info(c),modules*,main(c))
 
 defn remove-unknowns-w (w:Width) -> Width :
    match(w) :
-      (w:UnknownWidth) : VarWidth(firrtl-gensym(`w)) 
+      (w:UnknownWidth) : VarWidth(firrtl-gensym(`w,width-name-hash))
       (w) : w
 defn remove-unknowns (t:Type) -> Type : mapr(remove-unknowns-w,t)
 
@@ -1758,7 +1811,7 @@ public defmethod name (b:Inline) -> String : "Inline Instances"
 public defmethod short-name (b:Inline) -> String : "inline-instances"
 
 defn inline-instances (c:Circuit) :
-   val h = HashTable<Symbol,Module>(symbol-hash)
+   val h = HashTable<Symbol,InModule>(symbol-hash)
    val h-s = HashTable<Symbol,Stmt>(symbol-hash)
    defn inline-inst (s:Stmt) -> Stmt :
       match(map(inline-inst,s)) :
@@ -1781,30 +1834,32 @@ defn inline-instances (c:Circuit) :
          (e:WSubfield) : 
             match(kind(exp(e) as WRef)) :
                (k:InstanceKind) : 
-                  WRef(symbol-join([name(exp(e) as WRef) "_" name(e)]),type(e),k,gender(e))
+                  WRef(symbol-join([name(exp(e) as WRef) expand-delin name(e)]),type(e),k,gender(e))
                (k:MemKind) : e
          (e) : e
-   defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n "_" ref])
+   defn rename (ref:Symbol,n:Symbol) -> Symbol : symbol-join([n expand-delin ref])
    defn rename-e (e:Expression,n:Symbol) -> Expression :
       match(map(rename-e{_,n},e)) :
          (e:WRef) : WRef(rename(name(e),n),type(e),kind(e),gender(e))
          (e:WSubfield) : 
             match(kind(exp(e) as WRef)) :
                (k:InstanceKind) : 
-                  WRef(symbol-join([name(exp(e) as WRef) "_" name(e)]),type(e),k,gender(e))
+                  WRef(symbol-join([name(exp(e) as WRef) expand-delin name(e)]),type(e),k,gender(e))
                (k:MemKind) : e
          (e) : e
    defn rename-s (s:Stmt,n:Symbol) -> Stmt :
       map{rename-e{_,n},_} $ match(map(rename-s{_,n},s)) :
          (s:DefWire) : DefWire(info(s),rename(name(s),n),type(s))
          (s:DefInstance) : error("Shouldn't be here")
-         (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s))
+         (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s))
          (s:DefNode) : DefNode(info(s),rename(name(s),n),value(s))
          (s) : s
    for m in modules(c) do :
-      h[name(m)] = m
-   val top = (for m in modules(c) find : name(m) == main(c)) as Module
-   Circuit(info(c),list(Module(info(top),name(top),ports(top),inline-inst(body(top)))),main(c))
+      match(m) : 
+         (m:ExModule) : error("Cannot inline with external modules")
+         (m:InModule) : h[name(m)] = m
+   val top = (for m in modules(c) find : name(m) == main(c)) as InModule
+   Circuit(info(c),list(InModule(info(top),name(top),ports(top),inline-inst(body(top)))),main(c))
 
 
 ;================= Split Expressions ========================
@@ -1821,34 +1876,38 @@ defn full-name (e:Expression) -> Symbol :
       (e) : error("Non-supported expression.")
 
 defn split-exp (c:Circuit) :
-   defn split-exp-s (s:Stmt,v:Vector<Stmt>) -> False :
+   defn split-exp-s (s:Stmt,v:Vector<Stmt>,sh:HashTable<Symbol,Int>) -> False :
+      defn split-exp-e (e:Expression,n:Symbol|False,info:FileInfo) -> Expression :
+         match(map(split-exp-e{_,n,info},e)) :
+            (e:DoPrim) : 
+               val n* = 
+                  if n typeof False : firrtl-gensym(`T,sh)
+                  else : firrtl-gensym(symbol-join([n as Symbol gen-delin]),sh)
+               add(v,DefNode(info,n*,e))
+               WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER)
+            (e) : e
       match(s) :
          (s:Begin) : 
-            defn f (s:Stmt) -> False: split-exp-s(s,v)
+            defn f (s:Stmt) -> False: split-exp-s(s,v,sh)
             do(f,s)
          (s:Conditionally) : error("Shouldn't be here")
          (s:Connect) :
             match(loc(s)) :
-               (e:WritePort) : add(v,map(split-exp-e{_,v,full-name(exp(s)),info(s)},s))
-               (e) : add(v,map(split-exp-e{_,v,full-name(loc(s)),info(s)},s))
-         (s:DefNode) : add(v,map(split-exp-e{_,v,name(s),info(s)},s))
-         (s) : add(v,map(split-exp-e{_,v,false,info(s)},s))
+               (e:WritePort) : add(v,map(split-exp-e{_,full-name(exp(s)),info(s)},s))
+               (e) : add(v,map(split-exp-e{_,full-name(loc(s)),info(s)},s))
+         (s:DefNode) : add(v,map(split-exp-e{_,name(s),info(s)},s))
+         (s) : add(v,map(split-exp-e{_,false,info(s)},s))
       false
-   defn split-exp-e (e:Expression,v:Vector<Stmt>,n:Symbol|False,info:FileInfo) -> Expression :
-      match(map(split-exp-e{_,v,n,info},e)):
-         (e:DoPrim) : 
-            val n* = 
-               if n typeof False : firrtl-gensym(`T)
-               else : firrtl-gensym(symbol-join([n as Symbol `__]))
-            add(v,DefNode(info,n*,e))
-            WRef(n*,type(e),NodeKind(),UNKNOWN-GENDER)
-         (e) : e
 
    Circuit{info(c),_,main(c)} $
       for m in modules(c) map :
-         val v = Vector<Stmt>()
-         split-exp-s(body(m),v)
-         Module(info(m),name(m),ports(m),Begin(to-list(v)))
+         match(m) :
+            (m:InModule) :
+               val v = Vector<Stmt>()
+               val sh = get-sym-hash(m)
+               split-exp-s(body(m),v,sh)
+               InModule(info(m),name(m),ports(m),Begin(to-list(v)))
+            (m:ExModule) : m
 
 ;================= Bring to Real IR ========================
 ; Returns a new Circuit with only real IR nodes.
@@ -1874,5 +1933,60 @@ defn to-real-ir (c:Circuit) :
    Circuit(info(c),modules*, main(c)) where :
       val modules* =
          for m in modules(c) map :
-            Module(info(m),name(m), ports(m), to-stmt(body(m)))
+            match(m) :
+               (m:InModule) : InModule(info(m),name(m), ports(m), to-stmt(body(m)))
+               (m:ExModule) : m
+
+;================= Special Rename ========================
+; Returns a new Circuit with only real IR nodes.
+public defstruct SpecialRename <: Pass :
+   original-sym : Symbol
+   new-sym : Symbol
+public defmethod pass (b:SpecialRename) -> (Circuit -> Circuit) : special-rename{original-sym(b),new-sym(b),_:Circuit}
+public defmethod name (b:SpecialRename) -> String : "Special Rename"
+public defmethod short-name (b:SpecialRename) -> String : "special-rename"
+
+public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) :
+   defn rename (s:Symbol) -> Symbol :
+      val y = Vector<String>()
+      val os = to-string $ original-sym
+      val ns = to-string $ new-sym
+      defn rename (st:String) -> False :
+         if st == os : 
+            add(y,ns)
+         else if length(st) <= length(os) : 
+            add(y,st)
+         else :
+            if substring(st,0,length(os)) == os :
+               add(y,ns)
+               rename(substring(st,length(os),length(st)))
+            else : 
+               add(y,substring(st,0,1))
+               rename(substring(st,1,length(st)))
+      rename(to-string(s))
+      to-symbol $ string-join $ to-list(y)
+   defn to-exp (e:Expression) -> Expression :
+      match(map(to-exp,e)) :
+         (e:Ref) : Ref(rename(name(e)), type(e))
+         (e:Subfield) : Subfield(exp(e),rename(name(e)),type(e))
+         (e) : e
+   defn to-stmt (s:Stmt) -> Stmt :
+     match(map(to-exp,s)) :
+        (s:DefWire) : DefWire(info(s),rename(name(s)),type(s))
+        (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s))
+        (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s))
+        (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s))
+        (s:DefNode) : DefNode(info(s),rename(name(s)),value(s))
+        (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s))
+        (s) : map(to-stmt,s)
+
+   defn to-port (p:Port) -> Port : Port(info(p),rename(name(p)),direction(p),type(p))
+
+   Circuit(info(c),modules*, main(c)) where :
+      val modules* =
+         for m in modules(c) map :
+            match(m) :
+               (m:InModule) : InModule(info(m),name(m), map(to-port,ports(m)), to-stmt(body(m)))
+               (m:ExModule) : m
+
 
diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza
index 34ede86c..0e343d74 100644
--- a/src/main/stanza/primop.stanza
+++ b/src/main/stanza/primop.stanza
@@ -5,6 +5,7 @@ defpackage firrtl/primops :
   import firrtl/ir-utils
   import firrtl/passes
 
+
 public defn lower-and-type-primop (e:DoPrim) -> DoPrim :
    defn u () : UIntType(UnknownWidth())
    defn s () : SIntType(UnknownWidth())
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 19472573..bee10177 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -38,6 +38,11 @@ defn remove-subfield (e:Expression) -> Expression :
       (e:Subfield) : Ref(to-symbol $ string-join $ [emit(exp(e)) "_" name(e)],type(e))
       (e) : e
 
+definterface VKind
+defstruct WireKind <: VKind 
+defstruct RegKind <: VKind
+defstruct SeqMemKind <: VKind
+defstruct ComMemKind <: VKind
 
 ;============ Verilog Backend =============
 
@@ -109,7 +114,24 @@ defn emit (e:Expression) -> String :
                v = concat(v, [" ^ " emit(x)])
             v
 
-defn emit-module (m:Module) :
+defn emit-module (m:InModule) :
+   val h = HashTable<Symbol,VKind>(symbol-hash)
+   defn build-table (m:InModule) :
+      defn build-table (s:Stmt) -> Stmt :
+         match(map(build-table,s)) : 
+            (s:DefWire) : h[name(s)] = WireKind()
+            (s:DefMemory) : 
+               if seq?(s) : h[name(s)] = SeqMemKind()
+               else       : h[name(s)] = ComMemKind()
+            (s:Connect) : 
+               match(exp(s)) :
+                  (e:Register) : h[name(loc(s) as Ref)] = RegKind()
+                  (e) : false
+            (s) : false
+         s
+      build-table(body(m))
+   build-table(m)
+
    val wires = Vector<Streamable>()
    val regs = Vector<Streamable>()
    val inits = Vector<Streamable>()
@@ -117,39 +139,36 @@ defn emit-module (m:Module) :
    val updates = Vector<Streamable>()
    val insts = HashTable<Symbol,Symbol>(symbol-hash) ; inst -> module
    val inst-ports = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
+
+   val sh = get-sym-hash(m)
    
    defn emit-s (s:Stmt) :
       match(map(remove-subfield,s)) :
-         (s:DefWire) : add(wires,["wire " get-width(type(s)) " " name(s) ";"])
+         (s:DefWire) : 
+            if h[name(s)] == RegKind() : 
+               add(regs,["reg  " get-width(type(s)) " " name(s) ";"])
+            else :
+               add(wires,["wire " get-width(type(s)) " " name(s) ";"])
          (s:DefInstance) : 
             inst-ports[name(s)] = Vector<Streamable>()
             insts[name(s)] = name(module(s) as Ref)
             for f in fields(type(module(s)) as BundleType) do :
-               ;val sf = value(s) as Subfield
-               ;val e = exp(sf) as Ref
                val n* = to-symbol $ string-join $ [name(s) "_" name(f)]
                add(wires,["wire " get-width(type(f)) " " n* ";"])
                add(inst-ports[name(s)], ["." name(f) "( " n* " )"])
          (s:DefMemory) :
             val vtype = type(s) as VectorType
-            val innerwidth = 
-            add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
-            add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
-            add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"])
-         (s:DefNode) :
-            if value(s) typeof Register :
-               val reg = value(s) as Register
-               add(regs,["reg  " get-width(type(reg)) " " name(s) ";"])
-               add(inits,[name(s) " = {" width!(type(reg)) "{$random}};"])
-               add(updates,["if(" emit(enable(reg)) ") begin"])
-               add(updates,["  " name(s) " <= " emit(value(reg)) ";"])
-               add(updates,["end"])
-            else if value(s) typeof ReadPort :
-               val rp = value(s) as ReadPort
-               add(assigns,["assign " name(s) " = " emit(mem(rp)) "[" emit(index(rp)) "];"])
+            if seq?(s) :
+               add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
+               add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
+               add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"])
             else :
-               add(wires,["wire " get-width(type(value(s))) " " name(s) ";"])
-               add(assigns,["assign " name(s) " = " emit(value(s)) ";"])
+               add(regs,["reg  " get-width(type(vtype)) " " name(s) " [0:" size(vtype) "];"])
+               add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
+               add(inits,[name(s) " = {" width!(type(vtype)) "{$random}};"])
+         (s:DefNode) :
+            add(wires,["wire " get-width(type(value(s))) " " name(s) ";"])
+            add(assigns,["assign " name(s) " = " emit(value(s)) ";"])
          (s:Begin) : do(emit-s, body(s))
          (s:Connect) : 
             if loc(s) typeof WritePort :
@@ -158,7 +177,29 @@ defn emit-module (m:Module) :
                add(updates,["  " emit(mem(wp)) "[" emit(index(wp)) "] <= " emit(exp(s)) ";"])
                add(updates,["end"])
             else :
-               add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"])
+               if exp(s) typeof Register :
+                  val n = name(loc(s) as Ref)
+                  val reg = exp(s) as Register
+                  add(inits,[n " = {" width!(type(reg)) "{$random}};"])
+                  add(updates,["if(" emit(enable(reg)) ") begin"])
+                  add(updates,["  " n " <= " emit(value(reg)) ";"])
+                  add(updates,["end"])
+               else if exp(s) typeof ReadPort :
+                  val n = name(loc(s) as Ref)
+                  val rp = exp(s) as ReadPort
+                  match(h[name(mem(rp) as Ref)]) :
+                     (k:SeqMemKind) : 
+                        val index* = Ref(firrtl-gensym(name(index(rp) as Ref),sh),type(index(rp)))
+                        add(regs,[ "reg  " get-width(type(index*)) " " name(index*) ";"])
+                        add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"])
+                        add(updates,["if(" emit(enable(rp)) ") begin"])
+                        add(updates,["  " name(index*) " <= " emit(index(rp)) ";"])
+                        add(updates,["end"])
+                        add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index*) "];"])
+                     (k:ComMemKind) : 
+                        add(assigns,["assign " n " = " emit(mem(rp)) "[" emit(index(rp)) "];"])
+               else :
+                  add(assigns,["assign " emit(loc(s)) " = " emit(exp(s)) ";"])
          (s) : s 
    
    emit-s(body(m))
@@ -219,5 +260,8 @@ defn emit-module (m:Module) :
 public defn emit-verilog (file:String, c:Circuit) :
    with-output-file{file, _} $ fn () :
       for m in modules(c) do :
-         emit-module(m)
+         match(m) :
+            (m:InModule) : emit-module(m)
+            (m:ExModule) : false
+
    c
diff --git a/test/chisel3/ALUTop.fir b/test/chisel3/ALUTop.fir
new file mode 100644
index 00000000..b9386349
--- /dev/null
+++ b/test/chisel3/ALUTop.fir
@@ -0,0 +1,118 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit ALUTop : 
+  module ALU : 
+    input B : UInt<32>
+    output out : UInt<32>
+    output sum : UInt<32>
+    input A : UInt<32>
+    input alu_op : UInt<4>
+    
+    node shamt = bits(B, 4, 0)
+    node T_157 = add-wrap(A, B)
+    node T_158 = sub-wrap(A, B)
+    node T_159 = convert(A)
+    node T_160 = dshr(T_159, shamt)
+    node T_161 = as-UInt(T_160)
+    node T_162 = dshr(A, shamt)
+    node T_163 = dshl(A, shamt)
+    node T_164 = bits(T_163, 31, 0)
+    node T_165 = convert(A)
+    node T_166 = convert(B)
+    node T_167 = lt(T_165, T_166)
+    node T_168 = as-UInt(T_167)
+    node T_169 = lt(A, B)
+    node T_170 = as-UInt(T_169)
+    node T_171 = bit-and(A, B)
+    node T_172 = bit-or(A, B)
+    node T_173 = bit-xor(A, B)
+    node T_174 = eq(UInt<4>(10), alu_op)
+    node T_175 = mux(T_174, A, B)
+    node T_176 = eq(UInt<4>(4), alu_op)
+    node T_177 = mux(T_176, T_173, T_175)
+    node T_178 = eq(UInt<4>(3), alu_op)
+    node T_179 = mux(T_178, T_172, T_177)
+    node T_180 = eq(UInt<4>(2), alu_op)
+    node T_181 = mux(T_180, T_171, T_179)
+    node T_182 = eq(UInt<4>(7), alu_op)
+    node T_183 = mux(T_182, T_170, T_181)
+    node T_184 = eq(UInt<4>(5), alu_op)
+    node T_185 = mux(T_184, T_168, T_183)
+    node T_186 = eq(UInt<4>(6), alu_op)
+    node T_187 = mux(T_186, T_164, T_185)
+    node T_188 = eq(UInt<4>(8), alu_op)
+    node T_189 = mux(T_188, T_162, T_187)
+    node T_190 = eq(UInt<4>(9), alu_op)
+    node T_191 = mux(T_190, T_161, T_189)
+    node T_192 = eq(UInt<4>(1), alu_op)
+    node T_193 = mux(T_192, T_158, T_191)
+    node T_194 = eq(UInt<4>(0), alu_op)
+    node oot = mux(T_194, T_157, T_193)
+    node T_195 = bits(oot, 31, 0)
+    out := T_195
+    node T_196 = bit(alu_op, 0)
+    node T_197 = sub-wrap(UInt<1>(0), B)
+    node T_198 = mux(T_196, T_197, B)
+    node T_199 = add-wrap(A, T_198)
+    sum := T_199
+  module ALUdec : 
+    input opcode : UInt<7>
+    input funct : UInt<3>
+    input add_rshift_type : UInt<1>
+    output alu_op : UInt<4>
+    
+    node T_200 = mux(add_rshift_type, UInt<4>(1), UInt<4>(0))
+    node T_201 = mux(add_rshift_type, UInt<4>(9), UInt<4>(8))
+    node T_202 = eq(UInt<3>(5), funct)
+    node T_203 = mux(T_202, T_201, UInt<4>(15))
+    node T_204 = eq(UInt<3>(7), funct)
+    node T_205 = mux(T_204, UInt<4>(2), T_203)
+    node T_206 = eq(UInt<3>(6), funct)
+    node T_207 = mux(T_206, UInt<4>(3), T_205)
+    node T_208 = eq(UInt<3>(4), funct)
+    node T_209 = mux(T_208, UInt<4>(4), T_207)
+    node T_210 = eq(UInt<3>(3), funct)
+    node T_211 = mux(T_210, UInt<4>(7), T_209)
+    node T_212 = eq(UInt<3>(2), funct)
+    node T_213 = mux(T_212, UInt<4>(5), T_211)
+    node T_214 = eq(UInt<3>(1), funct)
+    node T_215 = mux(T_214, UInt<4>(6), T_213)
+    node T_216 = eq(UInt<3>(0), funct)
+    node alu_op1 = mux(T_216, T_200, T_215)
+    node T_217 = eq(UInt<7>(19), opcode)
+    node T_218 = mux(T_217, alu_op1, UInt<4>(15))
+    node T_219 = eq(UInt<7>(51), opcode)
+    node T_220 = mux(T_219, alu_op1, T_218)
+    node T_221 = eq(UInt<7>(3), opcode)
+    node T_222 = mux(T_221, UInt<4>(0), T_220)
+    node T_223 = eq(UInt<7>(35), opcode)
+    node T_224 = mux(T_223, UInt<4>(0), T_222)
+    node T_225 = eq(UInt<7>(99), opcode)
+    node T_226 = mux(T_225, UInt<4>(0), T_224)
+    node T_227 = eq(UInt<7>(103), opcode)
+    node T_228 = mux(T_227, UInt<4>(0), T_226)
+    node T_229 = eq(UInt<7>(111), opcode)
+    node T_230 = mux(T_229, UInt<4>(0), T_228)
+    node T_231 = eq(UInt<7>(23), opcode)
+    node T_232 = mux(T_231, UInt<4>(0), T_230)
+    node T_233 = eq(UInt<7>(55), opcode)
+    node alu_op2 = mux(T_233, UInt<4>(11), T_232)
+    alu_op := alu_op2
+  module ALUTop : 
+    input B : UInt<32>
+    output out : UInt<32>
+    input A : UInt<32>
+    input opcode : UInt<7>
+    input funct : UInt<3>
+    input add_rshift_type : UInt<1>
+    
+    inst alu of ALU
+    inst alu_dec of ALUdec
+    alu_dec.opcode := opcode
+    alu_dec.funct := funct
+    alu_dec.add_rshift_type := add_rshift_type
+    alu.A := A
+    alu.B := B
+    out := alu.out
+    alu.alu_op := alu_dec.alu_op
diff --git a/test/chisel3/BundleWire.fir b/test/chisel3/BundleWire.fir
new file mode 100644
index 00000000..2c2ad772
--- /dev/null
+++ b/test/chisel3/BundleWire.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit BundleWire : 
+  module BundleWire : 
+    input in : {x : UInt<32>, y : UInt<32>}
+    output outs : {x : UInt<32>, y : UInt<32>}[4]
+    
+    wire coords : {x : UInt<32>, y : UInt<32>}[4]
+    coords[0] := in
+    outs[0] := coords[0]
+    coords[1] := in
+    outs[1] := coords[1]
+    coords[2] := in
+    outs[2] := coords[2]
+    coords[3] := in
+    outs[3] := coords[3]
diff --git a/test/chisel3/ComplexAssign.fir b/test/chisel3/ComplexAssign.fir
new file mode 100644
index 00000000..c1dc41cd
--- /dev/null
+++ b/test/chisel3/ComplexAssign.fir
@@ -0,0 +1,16 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit ComplexAssign : 
+  module ComplexAssign : 
+    input in : {re : UInt<10>, im : UInt<10>}
+    output out : {re : UInt<10>, im : UInt<10>}
+    input e : UInt<1>
+    when e : 
+      wire T_18 : {re : UInt<10>, im : UInt<10>}
+      T_18 := in
+      out.re := T_18.re
+      out.im := T_18.im
+    else : 
+      out.re := UInt<1>(0)
+      out.im := UInt<1>(0)
diff --git a/test/passes/jacktest/Core.fir b/test/chisel3/Core.fir
index 667f52f3..b81eb7e9 100644
--- a/test/passes/jacktest/Core.fir
+++ b/test/chisel3/Core.fir
@@ -1,5 +1,6 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
+
 circuit Core : 
   module ALU : 
     input B : UInt<32>
@@ -56,10 +57,10 @@ circuit Core :
     node T_1266 = add-wrap(A, T_1265)
     sum := T_1266
   module BrCond : 
+    input br_type : UInt<3>
     input rs1 : UInt<32>
     input rs2 : UInt<32>
     output taken : UInt<1>
-    input br_type : UInt<3>
     
     node eq = eq(rs1, rs2)
     node neq = bit-not(eq)
@@ -148,7 +149,7 @@ circuit Core :
     node T_1321 = cat(T_1318, T_1320)
     node Jimm = convert(T_1321)
     node T_1322 = bits(inst, 19, 15)
-    node T_1323 = Pad(T_1322, 32)
+    node T_1323 = pad(T_1322, 32)
     node Zimm = convert(T_1323)
     node T_1324 = eq(UInt<3>(3), sel)
     node T_1325 = mux(T_1324, Jimm, Zimm)
@@ -218,10 +219,10 @@ circuit Core :
         reg_status := T_1361
   module Datapath : 
     output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>}
-    output icache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
-    input ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, A_sel : UInt<1>, inst_type : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>}
+    input ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>}
+    output icache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>}
+    output dcache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>}
     input stall : UInt<1>
-    output dcache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
     
     inst alu of ALU
     inst brCond of BrCond
@@ -330,11 +331,11 @@ circuit Core :
     node lshift = dshr(dcache.dout, loffset)
     node T_1412 = bits(lshift, 15, 0)
     node T_1413 = convert(T_1412)
-    node T_1414 = Pad(T_1413, 32)
+    node T_1414 = pad(T_1413, 32)
     node T_1415 = as-UInt(T_1414)
     node T_1416 = bits(lshift, 7, 0)
     node T_1417 = convert(T_1416)
-    node T_1418 = Pad(T_1417, 32)
+    node T_1418 = pad(T_1417, 32)
     node T_1419 = as-UInt(T_1418)
     node T_1420 = bits(lshift, 15, 0)
     node T_1421 = bits(lshift, 7, 0)
@@ -363,7 +364,7 @@ circuit Core :
     regFile.waddr := ex_rd_addr
     regFile.wdata := regWrite
   module Control : 
-    output ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, A_sel : UInt<1>, inst_type : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>}
+    output ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>}
     
     node T_1436 = bit-and(UInt<7>(127), ctrl.inst)
     node T_1437 = eq(T_1436, UInt<6>(55))
@@ -1009,9 +1010,9 @@ circuit Core :
     ctrl.csr_cmd := csr_cmd
   module Core : 
     output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>}
-    output icache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
+    output icache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>}
+    output dcache : {re : UInt<1>, addr : UInt<32>, flip dout : UInt<32>, we : UInt<4>, din : UInt<32>}
     input stall : UInt<1>
-    output dcache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
     
     inst dpath of Datapath
     inst ctrl of Control
diff --git a/test/chisel3/Counter.fir b/test/chisel3/Counter.fir
new file mode 100644
index 00000000..6f04dfb9
--- /dev/null
+++ b/test/chisel3/Counter.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit Counter : 
+  module Counter : 
+    input inc : UInt<1>
+    output tot : UInt<8>
+    input amt : UInt<4>
+    
+    reg T_13 : UInt<8>
+    on-reset T_13 := UInt<8>(0)
+    when inc : 
+      node T_14 = add-wrap(T_13, amt)
+      node T_15 = gt(T_14, UInt<8>(255))
+      node T_16 = mux(T_15, UInt<1>(0), T_14)
+      T_13 := T_16
+    tot := T_13
diff --git a/test/chisel3/EnableShiftRegister.fir b/test/chisel3/EnableShiftRegister.fir
new file mode 100644
index 00000000..795b03e4
--- /dev/null
+++ b/test/chisel3/EnableShiftRegister.fir
@@ -0,0 +1,23 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit EnableShiftRegister : 
+  module EnableShiftRegister : 
+    input in : UInt<4>
+    output out : UInt<4>
+    input shift : UInt<1>
+    
+    reg r0 : UInt<4>
+    on-reset r0 := UInt<4>(0)
+    reg r1 : UInt<4>
+    on-reset r1 := UInt<4>(0)
+    reg r2 : UInt<4>
+    on-reset r2 := UInt<4>(0)
+    reg r3 : UInt<4>
+    on-reset r3 := UInt<4>(0)
+    when shift : 
+      r0 := in
+      r1 := r0
+      r2 := r1
+      r3 := r2
+    out := r3
diff --git a/test/chisel3/GCD.fir b/test/chisel3/GCD.fir
new file mode 100644
index 00000000..d6f7d798
--- /dev/null
+++ b/test/chisel3/GCD.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit GCD : 
+  module GCD : 
+    output v : UInt<1>
+    input e : UInt<1>
+    output z : UInt<16>
+    input a : UInt<16>
+    input b : UInt<16>
+    
+    reg x : UInt<16>
+    reg y : UInt<16>
+    node T_17 = gt(x, y)
+    when T_17 : 
+      node T_18 = sub-wrap(x, y)
+      x := T_18
+    else : 
+      node T_19 = sub-wrap(y, x)
+      y := T_19
+    when e : 
+      x := a
+      y := b
+    z := x
+    node T_20 = eq(y, UInt<1>(0))
+    v := T_20
diff --git a/test/chisel3/ModuleWire.fir b/test/chisel3/ModuleWire.fir
new file mode 100644
index 00000000..fefe42bd
--- /dev/null
+++ b/test/chisel3/ModuleWire.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit ModuleWire : 
+  module Inc : 
+    input in : UInt<32>
+    output out : UInt<32>
+    
+    node T_12 = add-wrap(in, UInt<1>(1))
+    out := T_12
+  module ModuleWire : 
+    input in : UInt<32>
+    output out : UInt<32>
+    
+    inst T_13 of Inc
+    T_13.in := in
+    out := T_13.out
diff --git a/test/chisel3/Risc.fir b/test/chisel3/Risc.fir
new file mode 100644
index 00000000..bd02bac3
--- /dev/null
+++ b/test/chisel3/Risc.fir
@@ -0,0 +1,53 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit Risc : 
+  module Risc : 
+    output out : UInt<32>
+    output valid : UInt<1>
+    input boot : UInt<1>
+    input isWr : UInt<1>
+    input wrAddr : UInt<8>
+    input wrData : UInt<32>
+    
+    mem file : UInt<32>[256]
+    mem code : UInt<32>[256]
+    reg pc : UInt<8>
+    on-reset pc := UInt<8>(0)
+    accessor inst = code[pc]
+    node op = bits(inst, 31, 24)
+    node rci = bits(inst, 23, 16)
+    node rai = bits(inst, 15, 8)
+    node rbi = bits(inst, 7, 0)
+    node T_51 = eq(rai, UInt<1>(0))
+    accessor T_52 = file[rai]
+    node ra = mux(T_51, UInt<1>(0), T_52)
+    node T_53 = eq(rbi, UInt<1>(0))
+    accessor T_54 = file[rbi]
+    node rb = mux(T_53, UInt<1>(0), T_54)
+    wire rc : UInt<32>
+    valid := UInt<1>(0)
+    out := UInt<1>(0)
+    rc := UInt<1>(0)
+    when isWr : 
+      accessor T_55 = code[wrAddr]
+      T_55 := wrData
+    else : when boot : pc := UInt<1>(0)
+      else : 
+        node T_56 = eq(UInt<1>(0), op)
+        when T_56 : 
+          node T_57 = add-wrap(ra, rb)
+          rc := T_57
+        node T_58 = eq(UInt<1>(1), op)
+        when T_58 : 
+          node T_59 = shl(rai, 8)
+          node T_60 = bit-or(T_59, rbi)
+          rc := T_60
+        out := rc
+        node T_61 = eq(rci, UInt<8>(255))
+        when T_61 : valid := UInt<1>(1)
+        else : 
+          accessor T_62 = file[rci]
+          T_62 := rc
+        node T_63 = add-wrap(pc, UInt<1>(1))
+        pc := T_63
diff --git a/test/chisel3/Rom.fir b/test/chisel3/Rom.fir
new file mode 100644
index 00000000..8e80b7d4
--- /dev/null
+++ b/test/chisel3/Rom.fir
@@ -0,0 +1,27 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit Rom : 
+  module Rom : 
+    output out : UInt<5>
+    input addr : UInt<4>
+    
+    wire r : UInt<5>[16]
+    r[0] := UInt<5>(0)
+    r[1] := UInt<5>(2)
+    r[2] := UInt<5>(4)
+    r[3] := UInt<5>(6)
+    r[4] := UInt<5>(8)
+    r[5] := UInt<5>(10)
+    r[6] := UInt<5>(12)
+    r[7] := UInt<5>(14)
+    r[8] := UInt<5>(16)
+    r[9] := UInt<5>(18)
+    r[10] := UInt<5>(20)
+    r[11] := UInt<5>(22)
+    r[12] := UInt<5>(24)
+    r[13] := UInt<5>(26)
+    r[14] := UInt<5>(28)
+    r[15] := UInt<5>(30)
+    accessor T_39 = r[addr]
+    out := T_39
diff --git a/test/chisel3/Tbl.fir b/test/chisel3/Tbl.fir
new file mode 100644
index 00000000..d64916f1
--- /dev/null
+++ b/test/chisel3/Tbl.fir
@@ -0,0 +1,19 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit Tbl : 
+  module Tbl : 
+    input i : UInt<16>
+    input d : UInt<16>
+    output o : UInt<16>
+    input we : UInt<1>
+    
+    mem m : UInt<10>[256]
+    o := UInt<1>(0)
+    when we : 
+      accessor T_13 = m[i]
+      node T_14 = bits(d, 9, 0)
+      T_13 := T_14
+    else : 
+      accessor T_15 = m[i]
+      o := T_15
diff --git a/test/passes/jacktest/Tile.fir b/test/chisel3/Tile.fir
index f74aa172..eeec18ee 100644
--- a/test/passes/jacktest/Tile.fir
+++ b/test/chisel3/Tile.fir
@@ -1,5 +1,6 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
 ;CHECK: Done!
+
 circuit Tile : 
   module ALU : 
     input B : UInt<32>
@@ -148,7 +149,7 @@ circuit Tile :
     node T_1651 = cat(T_1648, T_1650)
     node Jimm = convert(T_1651)
     node T_1652 = bits(inst, 19, 15)
-    node T_1653 = Pad(T_1652, 32)
+    node T_1653 = pad(T_1652, 32)
     node Zimm = convert(T_1653)
     node T_1654 = eq(UInt<3>(3), sel)
     node T_1655 = mux(T_1654, Jimm, Zimm)
@@ -218,10 +219,10 @@ circuit Tile :
         reg_status := T_1691
   module Datapath : 
     output host : {status : UInt<32>, flip hid : UInt<1>, tohost : UInt<32>}
-    input ctrl : {flip inst : UInt<32>, inst_type : UInt<1>, A_sel : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, flip stall : UInt<1>}
     input stall : UInt<1>
     output icache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
     output dcache : {re : UInt<1>, flip dout : UInt<32>, we : UInt<4>, addr : UInt<32>, din : UInt<32>}
+    input ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, inst_re : UInt<1>, inst_type : UInt<1>, pc_sel : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>}
     
     inst alu of ALU
     inst brCond of BrCond
@@ -330,11 +331,11 @@ circuit Tile :
     node lshift = dshr(dcache.dout, loffset)
     node T_1742 = bits(lshift, 15, 0)
     node T_1743 = convert(T_1742)
-    node T_1744 = Pad(T_1743, 32)
+    node T_1744 = pad(T_1743, 32)
     node T_1745 = as-UInt(T_1744)
     node T_1746 = bits(lshift, 7, 0)
     node T_1747 = convert(T_1746)
-    node T_1748 = Pad(T_1747, 32)
+    node T_1748 = pad(T_1747, 32)
     node T_1749 = as-UInt(T_1748)
     node T_1750 = bits(lshift, 15, 0)
     node T_1751 = bits(lshift, 7, 0)
@@ -363,7 +364,7 @@ circuit Tile :
     regFile.waddr := ex_rd_addr
     regFile.wdata := regWrite
   module Control : 
-    output ctrl : {flip inst : UInt<32>, inst_type : UInt<1>, A_sel : UInt<1>, pc_sel : UInt<1>, inst_re : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, flip stall : UInt<1>}
+    output ctrl : {flip inst : UInt<32>, flip stall : UInt<1>, inst_re : UInt<1>, inst_type : UInt<1>, pc_sel : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>, data_re : UInt<1>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>}
     
     node T_1766 = bit-and(UInt<7>(127), ctrl.inst)
     node T_1767 = eq(T_1766, UInt<6>(55))
diff --git a/test/chisel3/UIntOps.fir b/test/chisel3/UIntOps.fir
new file mode 100644
index 00000000..9b219523
--- /dev/null
+++ b/test/chisel3/UIntOps.fir
@@ -0,0 +1,51 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit UIntOps : 
+  module UIntOps : 
+    input a : UInt<16>
+    input b : UInt<16>
+    output addout : UInt<16>
+    output subout : UInt<16>
+    output timesout : UInt<16>
+    output divout : UInt<16>
+    output modout : UInt<16>
+    output lshiftout : UInt<16>
+    output rshiftout : UInt<16>
+    output lessout : UInt<1>
+    output greatout : UInt<1>
+    output eqout : UInt<1>
+    output noteqout : UInt<1>
+    output lesseqout : UInt<1>
+    output greateqout : UInt<1>
+    
+    node T_38 = add-wrap(a, b)
+    addout := T_38
+    node T_39 = sub-wrap(a, b)
+    subout := T_39
+    node T_40 = mul(a, b)
+    node T_41 = bits(T_40, 15, 0)
+    timesout := T_41
+    node T_42 = eq(b, UInt<1>(0))
+    node T_43 = mux(T_42, UInt<1>(1), b)
+    node T_44 = div(a, T_43)
+    divout := T_44
+    modout := UInt<1>(0)
+    node T_45 = bits(b, 3, 0)
+    node T_46 = dshl(a, T_45)
+    node T_47 = bits(T_46, 15, 0)
+    lshiftout := T_47
+    node T_48 = dshr(a, b)
+    rshiftout := T_48
+    node T_49 = lt(a, b)
+    lessout := T_49
+    node T_50 = gt(a, b)
+    greatout := T_50
+    node T_51 = eq(a, b)
+    eqout := T_51
+    node T_52 = neq(a, b)
+    noteqout := T_52
+    node T_53 = leq(a, b)
+    lesseqout := T_53
+    node T_54 = geq(a, b)
+    greateqout := T_54
diff --git a/test/chisel3/VendingMachine.fir b/test/chisel3/VendingMachine.fir
new file mode 100644
index 00000000..a1149dbc
--- /dev/null
+++ b/test/chisel3/VendingMachine.fir
@@ -0,0 +1,31 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+
+circuit VendingMachine : 
+  module VendingMachine : 
+    output valid : UInt<1>
+    input nickel : UInt<1>
+    input dime : UInt<1>
+    
+    reg state : UInt<3>
+    on-reset state := UInt<3>(0)
+    node T_22 = eq(state, UInt<3>(0))
+    when T_22 : 
+      when nickel : state := UInt<3>(1)
+      when dime : state := UInt<3>(2)
+    node T_23 = eq(state, UInt<3>(1))
+    when T_23 : 
+      when nickel : state := UInt<3>(2)
+      when dime : state := UInt<3>(3)
+    node T_24 = eq(state, UInt<3>(2))
+    when T_24 : 
+      when nickel : state := UInt<3>(3)
+      when dime : state := UInt<3>(4)
+    node T_25 = eq(state, UInt<3>(3))
+    when T_25 : 
+      when nickel : state := UInt<3>(4)
+      when dime : state := UInt<3>(4)
+    node T_26 = eq(state, UInt<3>(4))
+    when T_26 : state := UInt<3>(0)
+    node T_27 = eq(state, UInt<3>(4))
+    valid := T_27
diff --git a/test/custom/when-coverage/gcd.fir b/test/custom/when-coverage/gcd.fir
new file mode 100644
index 00000000..d3e9d35b
--- /dev/null
+++ b/test/custom/when-coverage/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl -i %s -o %s.v -X verilute -s coverage -s when-scope -p c | tee %s.out | FileCheck %s
+
+;CHECK: Verilog
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap(x, y)
+   module gcd :
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
+      reg x : UInt
+      reg y : UInt
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
+      when gt(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := eq(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt<16>
+      input b : UInt<16>
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+;CHECK: Done!
+
diff --git a/test/errors/high-form/Flip-Mem.fir b/test/errors/high-form/Flip-Mem.fir
index 662fc6f1..5725aa90 100644
--- a/test/errors/high-form/Flip-Mem.fir
+++ b/test/errors/high-form/Flip-Mem.fir
@@ -1,6 +1,8 @@
 ; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-; CHECK: Memory m cannot be a bundle type with flips.
+; CHECK: Memory m-c cannot be a bundle type with flips.
+; CHECK: Memory m-s cannot be a bundle type with flips.
 
 circuit Flip-Mem : 
   module Flip-Mem : 
-    mem m : {x : UInt<3>, flip y : UInt<5>}[10]
+    cmem m-c : {x : UInt<3>, flip y : UInt<5>}[10]
+    smem m-s : {x : UInt<3>, flip y : UInt<5>}[10]
diff --git a/test/errors/high-form/NegVecSize.fir b/test/errors/high-form/NegVecSize.fir
new file mode 100644
index 00000000..16fae565
--- /dev/null
+++ b/test/errors/high-form/NegVecSize.fir
@@ -0,0 +1,7 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Vector type size cannot be negative
+
+circuit Top : 
+  module Top : 
+    wire x : UInt<3>[-5]
+
diff --git a/test/errors/high-form/NegWidth.fir b/test/errors/high-form/NegWidth.fir
new file mode 100644
index 00000000..3f305301
--- /dev/null
+++ b/test/errors/high-form/NegWidth.fir
@@ -0,0 +1,7 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Width cannot be negative.
+
+circuit Top : 
+  module Top : 
+    wire x : UInt<-3>
+
diff --git a/test/errors/high-form/NumArgs.fir b/test/errors/high-form/NumArgs.fir
new file mode 100644
index 00000000..4dc8ad46
--- /dev/null
+++ b/test/errors/high-form/NumArgs.fir
@@ -0,0 +1,11 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Primop mux requires 3 expression arguments.
+; CHECK: Primop add requires 2 expression arguments.
+; CHECK: Primop bits requires 2 integer arguments.
+
+circuit Top : 
+  module Top : 
+    node x = mux(UInt(1),UInt(1))
+    node y = add(SInt(1),UInt(1),UInt(1))
+    node z = bits(UInt(1),1,2,3)
+
diff --git a/test/errors/type/NodeWithFlips.fir b/test/errors/type/NodeWithFlips.fir
new file mode 100644
index 00000000..1342f78d
--- /dev/null
+++ b/test/errors/type/NodeWithFlips.fir
@@ -0,0 +1,8 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Node cannot be a bundle type with flips.
+
+circuit Top : 
+  module Top : 
+    wire x : {x : UInt, flip y : UInt}
+    node z = x
+
diff --git a/test/errors/type/Primop.fir b/test/errors/type/Primop.fir
new file mode 100644
index 00000000..b3a5dbc6
--- /dev/null
+++ b/test/errors/type/Primop.fir
@@ -0,0 +1,15 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+; CHECK: Primop mux requires all operands to have the same type.
+; CHECK: Primop add cannot operate on non-ground types.
+; CHECK: Primop add cannot operate on non-ground types.
+; CHECK: Primop bits requires all arguments to be UInt type.
+; CHECK: Primop mux requires argument SInt(1) to be a UInt type.
+
+circuit Top : 
+  module Top :
+    node x = mux(UInt(1),SInt(1),UInt(1))
+    wire a : { q : UInt<1> }
+    node y = add(a,a)
+    node z = bits(SInt<10>(-1),1,2)
+    node zz = mux(SInt(1),UInt(1),UInt(1))
+
diff --git a/test/features/BulkConnect.fir b/test/features/BulkConnect.fir
new file mode 100644
index 00000000..f78ba45b
--- /dev/null
+++ b/test/features/BulkConnect.fir
@@ -0,0 +1,28 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
+;CHECK: Lower To Ground
+circuit Top : 
+  module Top : 
+    wire a : { w : UInt<42>, x : UInt<10>, flip y : UInt<42>, z : SInt<42>}
+    wire b : { w : UInt<42>, x : UInt<20>, y : UInt<42>, z : UInt<42>}
+    a <> b 
+    ; CHECK:     a$w := b$w
+    ; CHECK:     a$x := b$x
+    ; CHECK-NOT: a$y := b$y
+    ; CHECK-NOT: b$y := a$y
+    ; CHECK-NOT: a$z := b$z
+    
+
+    wire c : { x : { y : UInt<1>, z : UInt<1>}}[4]
+    wire d : { x : { y : UInt<1>}}[2]
+    c <> d
+    ; CHECK:     c$0$x$y := d$0$x$y
+    ; CHECK:     c$1$x$y := d$1$x$y
+    ; CHECK-NOT: c$2$x$y := d$2$x$y
+    ; CHECK-NOT: c$3$x$y := d$3$x$y
+    ; CHECK-NOT: c$0$x$z := d$0$x$z
+    ; CHECK-NOT: c$1$x$z := d$1$x$z
+    ; CHECK-NOT: c$2$x$z := d$2$x$z
+    ; CHECK-NOT: c$3$x$z := d$3$x$z
+
+;CHECK: Finished Lower To Ground
+;CHECK: Done!
diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir
new file mode 100644
index 00000000..b47b14ab
--- /dev/null
+++ b/test/features/ExModule.fir
@@ -0,0 +1,14 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+circuit Top : 
+  module Top : 
+    output z : UInt<4>
+    inst i of BlackBox
+    i.x := UInt(1)
+    i.y := UInt(2)
+    z := i.z
+  exmodule BlackBox :
+    input x : UInt<4>
+    input y : UInt<4>
+    output z : UInt<4>
+
+;CHECK: Done!
diff --git a/test/features/SeqMem.fir b/test/features/SeqMem.fir
new file mode 100644
index 00000000..998df8c9
--- /dev/null
+++ b/test/features/SeqMem.fir
@@ -0,0 +1,22 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c | tee %s.out | FileCheck %s
+;CHECK: Done!
+circuit Top : 
+  module Top : 
+    wire i : UInt<5>
+    wire i0 : UInt<5>
+    wire j : UInt<128>
+
+    i0 := UInt(10)
+
+    cmem m-com : UInt<128>[32]
+    accessor r-com = m-com[i]
+    accessor w-com = m-com[i]
+    j := r-com
+    w-com := j
+
+
+    smem m-seq : UInt<128>[32]
+    accessor r-seq = m-seq[i]
+    accessor w-seq = m-seq[i]
+    j := r-seq
+    w-seq := j
diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index cbde1486..eb396bcf 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -3,7 +3,7 @@
 ;CHECK: Expand Accessors
 circuit top :
    module top :
-      mem m : UInt<32>[2][2][2]
+      cmem m : UInt<32>[2][2][2]
       wire i : UInt<4>
       i := UInt(1)
       accessor a = m[i] ;CHECK: accessor a = m[i]
diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir
index 901ab4e6..9d375087 100644
--- a/test/passes/expand-connect-indexed/bundle-vecs.fir
+++ b/test/passes/expand-connect-indexed/bundle-vecs.fir
@@ -7,23 +7,23 @@ circuit top :
       wire j : UInt
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
-      ; CHECK: wire a_0_x : UInt<32>
-      ; CHECK: wire a_0_y : UInt<32>
-      ; CHECK: wire a_1_x : UInt<32>
-      ; CHECK: wire a_1_y : UInt<32>
+      ; CHECK: wire a$0$x : UInt<32>
+      ; CHECK: wire a$0$y : UInt<32>
+      ; CHECK: wire a$1$x : UInt<32>
+      ; CHECK: wire a$1$y : UInt<32>
 
       accessor b = a[i]
-      ; CHECK: wire b_x : UInt<32>
-      ; CHECK: wire b_y : UInt<32>
-      ; CHECK: b_x := a_0_x
-      ; CHECK: node b_x__0 = i
-      ; CHECK: when eq(b_x__0, UInt(1)) :
-      ; CHECK:    b_x := a_1_x      
-      ; CHECK: node b_y__0 = i
-      ; CHECK: when eq(b_y__0, UInt(0)) :
-      ; CHECK:    a_0_y := b_y      
-      ; CHECK: when eq(b_y__0, UInt(1)) :
-      ; CHECK:    a_1_y := b_y      
+      ; CHECK: wire b$x : UInt<32>
+      ; CHECK: wire b$y : UInt<32>
+      ; CHECK: b$x := a$0$x
+      ; CHECK: node i#0 = i
+      ; CHECK: when eq(i#0, UInt(1)) :
+      ; CHECK:    b$x := a$1$x      
+      ; CHECK: node i#1 = i
+      ; CHECK: when eq(i#1, UInt(0)) :
+      ; CHECK:    a$0$y := b$y      
+      ; CHECK: when eq(i#1, UInt(1)) :
+      ; CHECK:    a$1$y := b$y      
       j := b.x
       
 ; CHECK: Finished Expand Indexed Connects
diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir
index c51604eb..4f8c31e2 100644
--- a/test/passes/expand-whens/bundle-init.fir
+++ b/test/passes/expand-whens/bundle-init.fir
@@ -15,11 +15,11 @@ circuit top :
       r.y := b
       on-reset r := w
 
-; CHECK: node r_x = Register(mux(reset, w_x, a), UInt(1))
-; CHECK: node r_y = Register(b, UInt(1))
+; CHECK: r$x := Register(mux(reset, w$x, a), UInt(1))
+; CHECK: r$y := Register(b, UInt(1))
 ; CHECK: a := UInt(1)
 ; CHECK: b := UInt(2)
-; CHECK: w_x := b
-; CHECK: w_y := mux(reset, r_y, a)   
+; CHECK: w$x := b
+; CHECK: w$y := mux(reset, r$y, a)   
       
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir
index 21a6f24b..f7ac8337 100644
--- a/test/passes/expand-whens/nested-whens.fir
+++ b/test/passes/expand-whens/nested-whens.fir
@@ -20,5 +20,5 @@ circuit top :
         on-reset r := y
         r := b
       r := z
-; CHECK: node r = Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1))
+; CHECK: r := Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1))
 ; CHECK: Finished Expand Whens
diff --git a/test/passes/expand-whens/one-when.fir b/test/passes/expand-whens/one-when.fir
index 718f1d4b..114e5b5b 100644
--- a/test/passes/expand-whens/one-when.fir
+++ b/test/passes/expand-whens/one-when.fir
@@ -3,7 +3,7 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m : UInt<1>[2]
+      cmem m : UInt<1>[2]
       wire i : UInt<1>
       wire p : UInt<1>
       wire j : UInt<1>
diff --git a/test/passes/expand-whens/two-when.fir b/test/passes/expand-whens/two-when.fir
index 7bee8444..fb537303 100644
--- a/test/passes/expand-whens/two-when.fir
+++ b/test/passes/expand-whens/two-when.fir
@@ -3,7 +3,7 @@
 ; CHECK: Expand Whens
 circuit top :
    module top :
-      mem m :{ x : UInt<1>, y : UInt<1> }[2] 
+      cmem m :{ x : UInt<1>, y : UInt<1> }[2] 
       wire i : UInt<1>
       wire p : UInt<1>
       wire q : { x : UInt<1>, y : UInt<1> }
diff --git a/test/passes/jacktest/Control.fir b/test/passes/jacktest/Control.fir
deleted file mode 100644
index b0acfc50..00000000
--- a/test/passes/jacktest/Control.fir
+++ /dev/null
@@ -1,648 +0,0 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
-circuit Control : 
-  module Control : 
-    output ctrl : {flip inst : UInt<32>, st_type : UInt<2>, ld_type : UInt<3>, wb_sel : UInt<2>, wb_en : UInt<1>, csr_cmd : UInt<2>, pc_sel : UInt<1>, inst_re : UInt<1>, flip stall : UInt<1>, data_re : UInt<1>, inst_type : UInt<1>, A_sel : UInt<1>, B_sel : UInt<1>, imm_sel : UInt<3>, alu_op : UInt<4>, br_type : UInt<3>}
-    
-    node T_831 = bit-and(UInt<7>(127), ctrl.inst)
-    node T_832 = eq(T_831, UInt<6>(55))
-    node T_833 = bit-and(UInt<7>(127), ctrl.inst)
-    node T_834 = eq(T_833, UInt<5>(23))
-    node T_835 = bit-and(UInt<7>(127), ctrl.inst)
-    node T_836 = eq(T_835, UInt<7>(111))
-    node T_837 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_838 = eq(T_837, UInt<7>(103))
-    node T_839 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_840 = eq(T_839, UInt<7>(99))
-    node T_841 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_842 = eq(T_841, UInt<13>(4195))
-    node T_843 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_844 = eq(T_843, UInt<15>(16483))
-    node T_845 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_846 = eq(T_845, UInt<15>(20579))
-    node T_847 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_848 = eq(T_847, UInt<15>(24675))
-    node T_849 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_850 = eq(T_849, UInt<15>(28771))
-    node T_851 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_852 = eq(T_851, UInt<2>(3))
-    node T_853 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_854 = eq(T_853, UInt<13>(4099))
-    node T_855 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_856 = eq(T_855, UInt<14>(8195))
-    node T_857 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_858 = eq(T_857, UInt<15>(16387))
-    node T_859 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_860 = eq(T_859, UInt<15>(20483))
-    node T_861 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_862 = eq(T_861, UInt<6>(35))
-    node T_863 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_864 = eq(T_863, UInt<13>(4131))
-    node T_865 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_866 = eq(T_865, UInt<14>(8227))
-    node T_867 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_868 = eq(T_867, UInt<5>(19))
-    node T_869 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_870 = eq(T_869, UInt<14>(8211))
-    node T_871 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_872 = eq(T_871, UInt<14>(12307))
-    node T_873 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_874 = eq(T_873, UInt<15>(16403))
-    node T_875 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_876 = eq(T_875, UInt<15>(24595))
-    node T_877 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_878 = eq(T_877, UInt<15>(28691))
-    node T_879 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_880 = eq(T_879, UInt<13>(4115))
-    node T_881 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_882 = eq(T_881, UInt<15>(20499))
-    node T_883 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_884 = eq(T_883, UInt<31>(1073762323))
-    node T_885 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_886 = eq(T_885, UInt<6>(51))
-    node T_887 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_888 = eq(T_887, UInt<31>(1073741875))
-    node T_889 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_890 = eq(T_889, UInt<13>(4147))
-    node T_891 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_892 = eq(T_891, UInt<14>(8243))
-    node T_893 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_894 = eq(T_893, UInt<14>(12339))
-    node T_895 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_896 = eq(T_895, UInt<15>(16435))
-    node T_897 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_898 = eq(T_897, UInt<15>(20531))
-    node T_899 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_900 = eq(T_899, UInt<31>(1073762355))
-    node T_901 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_902 = eq(T_901, UInt<15>(24627))
-    node T_903 = bit-and(UInt<32>(4261441663), ctrl.inst)
-    node T_904 = eq(T_903, UInt<15>(28723))
-    node T_905 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_906 = eq(T_905, UInt<13>(4211))
-    node T_907 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_908 = eq(T_907, UInt<14>(8307))
-    node T_909 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_910 = eq(T_909, UInt<14>(12403))
-    node T_911 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_912 = eq(T_911, UInt<15>(20595))
-    node T_913 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_914 = eq(T_913, UInt<15>(24691))
-    node T_915 = bit-and(UInt<15>(28799), ctrl.inst)
-    node T_916 = eq(T_915, UInt<15>(28787))
-    node T_917 = mux(T_916, UInt<1>(0), UInt<1>(0))
-    node T_918 = mux(T_914, UInt<1>(0), T_917)
-    node T_919 = mux(T_912, UInt<1>(0), T_918)
-    node T_920 = mux(T_910, UInt<1>(0), T_919)
-    node T_921 = mux(T_908, UInt<1>(0), T_920)
-    node T_922 = mux(T_906, UInt<1>(0), T_921)
-    node T_923 = mux(T_904, UInt<1>(0), T_922)
-    node T_924 = mux(T_902, UInt<1>(0), T_923)
-    node T_925 = mux(T_900, UInt<1>(0), T_924)
-    node T_926 = mux(T_898, UInt<1>(0), T_925)
-    node T_927 = mux(T_896, UInt<1>(0), T_926)
-    node T_928 = mux(T_894, UInt<1>(0), T_927)
-    node T_929 = mux(T_892, UInt<1>(0), T_928)
-    node T_930 = mux(T_890, UInt<1>(0), T_929)
-    node T_931 = mux(T_888, UInt<1>(0), T_930)
-    node T_932 = mux(T_886, UInt<1>(0), T_931)
-    node T_933 = mux(T_884, UInt<1>(0), T_932)
-    node T_934 = mux(T_882, UInt<1>(0), T_933)
-    node T_935 = mux(T_880, UInt<1>(0), T_934)
-    node T_936 = mux(T_878, UInt<1>(0), T_935)
-    node T_937 = mux(T_876, UInt<1>(0), T_936)
-    node T_938 = mux(T_874, UInt<1>(0), T_937)
-    node T_939 = mux(T_872, UInt<1>(0), T_938)
-    node T_940 = mux(T_870, UInt<1>(0), T_939)
-    node T_941 = mux(T_868, UInt<1>(0), T_940)
-    node T_942 = mux(T_866, UInt<1>(0), T_941)
-    node T_943 = mux(T_864, UInt<1>(0), T_942)
-    node T_944 = mux(T_862, UInt<1>(0), T_943)
-    node T_945 = mux(T_860, UInt<1>(0), T_944)
-    node T_946 = mux(T_858, UInt<1>(0), T_945)
-    node T_947 = mux(T_856, UInt<1>(0), T_946)
-    node T_948 = mux(T_854, UInt<1>(0), T_947)
-    node T_949 = mux(T_852, UInt<1>(0), T_948)
-    node T_950 = mux(T_850, UInt<1>(0), T_949)
-    node T_951 = mux(T_848, UInt<1>(0), T_950)
-    node T_952 = mux(T_846, UInt<1>(0), T_951)
-    node T_953 = mux(T_844, UInt<1>(0), T_952)
-    node T_954 = mux(T_842, UInt<1>(0), T_953)
-    node T_955 = mux(T_840, UInt<1>(0), T_954)
-    node T_956 = mux(T_838, UInt<1>(1), T_955)
-    node T_957 = mux(T_836, UInt<1>(1), T_956)
-    node T_958 = mux(T_834, UInt<1>(0), T_957)
-    node T_959 = mux(T_832, UInt<1>(0), T_958)
-    node T_960 = mux(T_916, UInt<1>(1), UInt<1>(1))
-    node T_961 = mux(T_914, UInt<1>(1), T_960)
-    node T_962 = mux(T_912, UInt<1>(1), T_961)
-    node T_963 = mux(T_910, UInt<1>(0), T_962)
-    node T_964 = mux(T_908, UInt<1>(0), T_963)
-    node T_965 = mux(T_906, UInt<1>(0), T_964)
-    node T_966 = mux(T_904, UInt<1>(0), T_965)
-    node T_967 = mux(T_902, UInt<1>(0), T_966)
-    node T_968 = mux(T_900, UInt<1>(0), T_967)
-    node T_969 = mux(T_898, UInt<1>(0), T_968)
-    node T_970 = mux(T_896, UInt<1>(0), T_969)
-    node T_971 = mux(T_894, UInt<1>(0), T_970)
-    node T_972 = mux(T_892, UInt<1>(0), T_971)
-    node T_973 = mux(T_890, UInt<1>(0), T_972)
-    node T_974 = mux(T_888, UInt<1>(0), T_973)
-    node T_975 = mux(T_886, UInt<1>(0), T_974)
-    node T_976 = mux(T_884, UInt<1>(0), T_975)
-    node T_977 = mux(T_882, UInt<1>(0), T_976)
-    node T_978 = mux(T_880, UInt<1>(0), T_977)
-    node T_979 = mux(T_878, UInt<1>(0), T_978)
-    node T_980 = mux(T_876, UInt<1>(0), T_979)
-    node T_981 = mux(T_874, UInt<1>(0), T_980)
-    node T_982 = mux(T_872, UInt<1>(0), T_981)
-    node T_983 = mux(T_870, UInt<1>(0), T_982)
-    node T_984 = mux(T_868, UInt<1>(0), T_983)
-    node T_985 = mux(T_866, UInt<1>(0), T_984)
-    node T_986 = mux(T_864, UInt<1>(0), T_985)
-    node T_987 = mux(T_862, UInt<1>(0), T_986)
-    node T_988 = mux(T_860, UInt<1>(0), T_987)
-    node T_989 = mux(T_858, UInt<1>(0), T_988)
-    node T_990 = mux(T_856, UInt<1>(0), T_989)
-    node T_991 = mux(T_854, UInt<1>(0), T_990)
-    node T_992 = mux(T_852, UInt<1>(0), T_991)
-    node T_993 = mux(T_850, UInt<1>(1), T_992)
-    node T_994 = mux(T_848, UInt<1>(1), T_993)
-    node T_995 = mux(T_846, UInt<1>(1), T_994)
-    node T_996 = mux(T_844, UInt<1>(1), T_995)
-    node T_997 = mux(T_842, UInt<1>(1), T_996)
-    node T_998 = mux(T_840, UInt<1>(1), T_997)
-    node T_999 = mux(T_838, UInt<1>(0), T_998)
-    node T_1000 = mux(T_836, UInt<1>(1), T_999)
-    node T_1001 = mux(T_834, UInt<1>(1), T_1000)
-    node T_1002 = mux(T_832, UInt<1>(1), T_1001)
-    node T_1003 = mux(T_916, UInt<1>(1), UInt<1>(0))
-    node T_1004 = mux(T_914, UInt<1>(1), T_1003)
-    node T_1005 = mux(T_912, UInt<1>(1), T_1004)
-    node T_1006 = mux(T_910, UInt<1>(0), T_1005)
-    node T_1007 = mux(T_908, UInt<1>(0), T_1006)
-    node T_1008 = mux(T_906, UInt<1>(0), T_1007)
-    node T_1009 = mux(T_904, UInt<1>(0), T_1008)
-    node T_1010 = mux(T_902, UInt<1>(0), T_1009)
-    node T_1011 = mux(T_900, UInt<1>(0), T_1010)
-    node T_1012 = mux(T_898, UInt<1>(0), T_1011)
-    node T_1013 = mux(T_896, UInt<1>(0), T_1012)
-    node T_1014 = mux(T_894, UInt<1>(0), T_1013)
-    node T_1015 = mux(T_892, UInt<1>(0), T_1014)
-    node T_1016 = mux(T_890, UInt<1>(0), T_1015)
-    node T_1017 = mux(T_888, UInt<1>(0), T_1016)
-    node T_1018 = mux(T_886, UInt<1>(0), T_1017)
-    node T_1019 = mux(T_884, UInt<1>(1), T_1018)
-    node T_1020 = mux(T_882, UInt<1>(1), T_1019)
-    node T_1021 = mux(T_880, UInt<1>(1), T_1020)
-    node T_1022 = mux(T_878, UInt<1>(1), T_1021)
-    node T_1023 = mux(T_876, UInt<1>(1), T_1022)
-    node T_1024 = mux(T_874, UInt<1>(1), T_1023)
-    node T_1025 = mux(T_872, UInt<1>(1), T_1024)
-    node T_1026 = mux(T_870, UInt<1>(1), T_1025)
-    node T_1027 = mux(T_868, UInt<1>(1), T_1026)
-    node T_1028 = mux(T_866, UInt<1>(1), T_1027)
-    node T_1029 = mux(T_864, UInt<1>(1), T_1028)
-    node T_1030 = mux(T_862, UInt<1>(1), T_1029)
-    node T_1031 = mux(T_860, UInt<1>(1), T_1030)
-    node T_1032 = mux(T_858, UInt<1>(1), T_1031)
-    node T_1033 = mux(T_856, UInt<1>(1), T_1032)
-    node T_1034 = mux(T_854, UInt<1>(1), T_1033)
-    node T_1035 = mux(T_852, UInt<1>(1), T_1034)
-    node T_1036 = mux(T_850, UInt<1>(1), T_1035)
-    node T_1037 = mux(T_848, UInt<1>(1), T_1036)
-    node T_1038 = mux(T_846, UInt<1>(1), T_1037)
-    node T_1039 = mux(T_844, UInt<1>(1), T_1038)
-    node T_1040 = mux(T_842, UInt<1>(1), T_1039)
-    node T_1041 = mux(T_840, UInt<1>(1), T_1040)
-    node T_1042 = mux(T_838, UInt<1>(1), T_1041)
-    node T_1043 = mux(T_836, UInt<1>(1), T_1042)
-    node T_1044 = mux(T_834, UInt<1>(1), T_1043)
-    node T_1045 = mux(T_832, UInt<1>(1), T_1044)
-    node T_1046 = mux(T_916, UInt<3>(5), UInt<3>(7))
-    node T_1047 = mux(T_914, UInt<3>(5), T_1046)
-    node T_1048 = mux(T_912, UInt<3>(5), T_1047)
-    node T_1049 = mux(T_910, UInt<3>(5), T_1048)
-    node T_1050 = mux(T_908, UInt<3>(5), T_1049)
-    node T_1051 = mux(T_906, UInt<3>(5), T_1050)
-    node T_1052 = mux(T_904, UInt<3>(7), T_1051)
-    node T_1053 = mux(T_902, UInt<3>(7), T_1052)
-    node T_1054 = mux(T_900, UInt<3>(7), T_1053)
-    node T_1055 = mux(T_898, UInt<3>(7), T_1054)
-    node T_1056 = mux(T_896, UInt<3>(7), T_1055)
-    node T_1057 = mux(T_894, UInt<3>(7), T_1056)
-    node T_1058 = mux(T_892, UInt<3>(7), T_1057)
-    node T_1059 = mux(T_890, UInt<3>(7), T_1058)
-    node T_1060 = mux(T_888, UInt<3>(7), T_1059)
-    node T_1061 = mux(T_886, UInt<3>(7), T_1060)
-    node T_1062 = mux(T_884, UInt<3>(0), T_1061)
-    node T_1063 = mux(T_882, UInt<3>(0), T_1062)
-    node T_1064 = mux(T_880, UInt<3>(0), T_1063)
-    node T_1065 = mux(T_878, UInt<3>(0), T_1064)
-    node T_1066 = mux(T_876, UInt<3>(0), T_1065)
-    node T_1067 = mux(T_874, UInt<3>(0), T_1066)
-    node T_1068 = mux(T_872, UInt<3>(0), T_1067)
-    node T_1069 = mux(T_870, UInt<3>(0), T_1068)
-    node T_1070 = mux(T_868, UInt<3>(0), T_1069)
-    node T_1071 = mux(T_866, UInt<3>(1), T_1070)
-    node T_1072 = mux(T_864, UInt<3>(1), T_1071)
-    node T_1073 = mux(T_862, UInt<3>(1), T_1072)
-    node T_1074 = mux(T_860, UInt<3>(0), T_1073)
-    node T_1075 = mux(T_858, UInt<3>(0), T_1074)
-    node T_1076 = mux(T_856, UInt<3>(0), T_1075)
-    node T_1077 = mux(T_854, UInt<3>(0), T_1076)
-    node T_1078 = mux(T_852, UInt<3>(0), T_1077)
-    node T_1079 = mux(T_850, UInt<3>(4), T_1078)
-    node T_1080 = mux(T_848, UInt<3>(4), T_1079)
-    node T_1081 = mux(T_846, UInt<3>(4), T_1080)
-    node T_1082 = mux(T_844, UInt<3>(4), T_1081)
-    node T_1083 = mux(T_842, UInt<3>(4), T_1082)
-    node T_1084 = mux(T_840, UInt<3>(4), T_1083)
-    node T_1085 = mux(T_838, UInt<3>(0), T_1084)
-    node T_1086 = mux(T_836, UInt<3>(3), T_1085)
-    node T_1087 = mux(T_834, UInt<3>(2), T_1086)
-    node T_1088 = mux(T_832, UInt<3>(2), T_1087)
-    node T_1089 = mux(T_916, UInt<4>(11), UInt<4>(15))
-    node T_1090 = mux(T_914, UInt<4>(11), T_1089)
-    node T_1091 = mux(T_912, UInt<4>(11), T_1090)
-    node T_1092 = mux(T_910, UInt<4>(10), T_1091)
-    node T_1093 = mux(T_908, UInt<4>(10), T_1092)
-    node T_1094 = mux(T_906, UInt<4>(10), T_1093)
-    node T_1095 = mux(T_904, UInt<4>(2), T_1094)
-    node T_1096 = mux(T_902, UInt<4>(3), T_1095)
-    node T_1097 = mux(T_900, UInt<4>(9), T_1096)
-    node T_1098 = mux(T_898, UInt<4>(8), T_1097)
-    node T_1099 = mux(T_896, UInt<4>(4), T_1098)
-    node T_1100 = mux(T_894, UInt<4>(7), T_1099)
-    node T_1101 = mux(T_892, UInt<4>(5), T_1100)
-    node T_1102 = mux(T_890, UInt<4>(6), T_1101)
-    node T_1103 = mux(T_888, UInt<4>(1), T_1102)
-    node T_1104 = mux(T_886, UInt<4>(0), T_1103)
-    node T_1105 = mux(T_884, UInt<4>(9), T_1104)
-    node T_1106 = mux(T_882, UInt<4>(8), T_1105)
-    node T_1107 = mux(T_880, UInt<4>(6), T_1106)
-    node T_1108 = mux(T_878, UInt<4>(2), T_1107)
-    node T_1109 = mux(T_876, UInt<4>(3), T_1108)
-    node T_1110 = mux(T_874, UInt<4>(4), T_1109)
-    node T_1111 = mux(T_872, UInt<4>(7), T_1110)
-    node T_1112 = mux(T_870, UInt<4>(5), T_1111)
-    node T_1113 = mux(T_868, UInt<4>(0), T_1112)
-    node T_1114 = mux(T_866, UInt<4>(0), T_1113)
-    node T_1115 = mux(T_864, UInt<4>(0), T_1114)
-    node T_1116 = mux(T_862, UInt<4>(0), T_1115)
-    node T_1117 = mux(T_860, UInt<4>(0), T_1116)
-    node T_1118 = mux(T_858, UInt<4>(0), T_1117)
-    node T_1119 = mux(T_856, UInt<4>(0), T_1118)
-    node T_1120 = mux(T_854, UInt<4>(0), T_1119)
-    node T_1121 = mux(T_852, UInt<4>(0), T_1120)
-    node T_1122 = mux(T_850, UInt<4>(0), T_1121)
-    node T_1123 = mux(T_848, UInt<4>(0), T_1122)
-    node T_1124 = mux(T_846, UInt<4>(0), T_1123)
-    node T_1125 = mux(T_844, UInt<4>(0), T_1124)
-    node T_1126 = mux(T_842, UInt<4>(0), T_1125)
-    node T_1127 = mux(T_840, UInt<4>(0), T_1126)
-    node T_1128 = mux(T_838, UInt<4>(0), T_1127)
-    node T_1129 = mux(T_836, UInt<4>(0), T_1128)
-    node T_1130 = mux(T_834, UInt<4>(0), T_1129)
-    node T_1131 = mux(T_832, UInt<4>(11), T_1130)
-    node T_1132 = mux(T_916, UInt<3>(7), UInt<3>(7))
-    node T_1133 = mux(T_914, UInt<3>(7), T_1132)
-    node T_1134 = mux(T_912, UInt<3>(7), T_1133)
-    node T_1135 = mux(T_910, UInt<3>(7), T_1134)
-    node T_1136 = mux(T_908, UInt<3>(7), T_1135)
-    node T_1137 = mux(T_906, UInt<3>(7), T_1136)
-    node T_1138 = mux(T_904, UInt<3>(7), T_1137)
-    node T_1139 = mux(T_902, UInt<3>(7), T_1138)
-    node T_1140 = mux(T_900, UInt<3>(7), T_1139)
-    node T_1141 = mux(T_898, UInt<3>(7), T_1140)
-    node T_1142 = mux(T_896, UInt<3>(7), T_1141)
-    node T_1143 = mux(T_894, UInt<3>(7), T_1142)
-    node T_1144 = mux(T_892, UInt<3>(7), T_1143)
-    node T_1145 = mux(T_890, UInt<3>(7), T_1144)
-    node T_1146 = mux(T_888, UInt<3>(7), T_1145)
-    node T_1147 = mux(T_886, UInt<3>(7), T_1146)
-    node T_1148 = mux(T_884, UInt<3>(7), T_1147)
-    node T_1149 = mux(T_882, UInt<3>(7), T_1148)
-    node T_1150 = mux(T_880, UInt<3>(7), T_1149)
-    node T_1151 = mux(T_878, UInt<3>(7), T_1150)
-    node T_1152 = mux(T_876, UInt<3>(7), T_1151)
-    node T_1153 = mux(T_874, UInt<3>(7), T_1152)
-    node T_1154 = mux(T_872, UInt<3>(7), T_1153)
-    node T_1155 = mux(T_870, UInt<3>(7), T_1154)
-    node T_1156 = mux(T_868, UInt<3>(7), T_1155)
-    node T_1157 = mux(T_866, UInt<3>(7), T_1156)
-    node T_1158 = mux(T_864, UInt<3>(7), T_1157)
-    node T_1159 = mux(T_862, UInt<3>(7), T_1158)
-    node T_1160 = mux(T_860, UInt<3>(7), T_1159)
-    node T_1161 = mux(T_858, UInt<3>(7), T_1160)
-    node T_1162 = mux(T_856, UInt<3>(7), T_1161)
-    node T_1163 = mux(T_854, UInt<3>(7), T_1162)
-    node T_1164 = mux(T_852, UInt<3>(7), T_1163)
-    node T_1165 = mux(T_850, UInt<3>(4), T_1164)
-    node T_1166 = mux(T_848, UInt<3>(0), T_1165)
-    node T_1167 = mux(T_846, UInt<3>(5), T_1166)
-    node T_1168 = mux(T_844, UInt<3>(1), T_1167)
-    node T_1169 = mux(T_842, UInt<3>(6), T_1168)
-    node T_1170 = mux(T_840, UInt<3>(2), T_1169)
-    node T_1171 = mux(T_838, UInt<3>(7), T_1170)
-    node T_1172 = mux(T_836, UInt<3>(7), T_1171)
-    node T_1173 = mux(T_834, UInt<3>(7), T_1172)
-    node T_1174 = mux(T_832, UInt<3>(7), T_1173)
-    node T_1175 = mux(T_916, UInt<1>(0), UInt<1>(0))
-    node T_1176 = mux(T_914, UInt<1>(0), T_1175)
-    node T_1177 = mux(T_912, UInt<1>(0), T_1176)
-    node T_1178 = mux(T_910, UInt<1>(0), T_1177)
-    node T_1179 = mux(T_908, UInt<1>(0), T_1178)
-    node T_1180 = mux(T_906, UInt<1>(0), T_1179)
-    node T_1181 = mux(T_904, UInt<1>(0), T_1180)
-    node T_1182 = mux(T_902, UInt<1>(0), T_1181)
-    node T_1183 = mux(T_900, UInt<1>(0), T_1182)
-    node T_1184 = mux(T_898, UInt<1>(0), T_1183)
-    node T_1185 = mux(T_896, UInt<1>(0), T_1184)
-    node T_1186 = mux(T_894, UInt<1>(0), T_1185)
-    node T_1187 = mux(T_892, UInt<1>(0), T_1186)
-    node T_1188 = mux(T_890, UInt<1>(0), T_1187)
-    node T_1189 = mux(T_888, UInt<1>(0), T_1188)
-    node T_1190 = mux(T_886, UInt<1>(0), T_1189)
-    node T_1191 = mux(T_884, UInt<1>(0), T_1190)
-    node T_1192 = mux(T_882, UInt<1>(0), T_1191)
-    node T_1193 = mux(T_880, UInt<1>(0), T_1192)
-    node T_1194 = mux(T_878, UInt<1>(0), T_1193)
-    node T_1195 = mux(T_876, UInt<1>(0), T_1194)
-    node T_1196 = mux(T_874, UInt<1>(0), T_1195)
-    node T_1197 = mux(T_872, UInt<1>(0), T_1196)
-    node T_1198 = mux(T_870, UInt<1>(0), T_1197)
-    node T_1199 = mux(T_868, UInt<1>(0), T_1198)
-    node T_1200 = mux(T_866, UInt<1>(0), T_1199)
-    node T_1201 = mux(T_864, UInt<1>(0), T_1200)
-    node T_1202 = mux(T_862, UInt<1>(0), T_1201)
-    node T_1203 = mux(T_860, UInt<1>(0), T_1202)
-    node T_1204 = mux(T_858, UInt<1>(0), T_1203)
-    node T_1205 = mux(T_856, UInt<1>(0), T_1204)
-    node T_1206 = mux(T_854, UInt<1>(0), T_1205)
-    node T_1207 = mux(T_852, UInt<1>(0), T_1206)
-    node T_1208 = mux(T_850, UInt<1>(0), T_1207)
-    node T_1209 = mux(T_848, UInt<1>(0), T_1208)
-    node T_1210 = mux(T_846, UInt<1>(0), T_1209)
-    node T_1211 = mux(T_844, UInt<1>(0), T_1210)
-    node T_1212 = mux(T_842, UInt<1>(0), T_1211)
-    node T_1213 = mux(T_840, UInt<1>(0), T_1212)
-    node T_1214 = mux(T_838, UInt<1>(1), T_1213)
-    node T_1215 = mux(T_836, UInt<1>(1), T_1214)
-    node T_1216 = mux(T_834, UInt<1>(0), T_1215)
-    node T_1217 = mux(T_832, UInt<1>(0), T_1216)
-    node T_1218 = mux(T_916, UInt<2>(3), UInt<2>(3))
-    node T_1219 = mux(T_914, UInt<2>(3), T_1218)
-    node T_1220 = mux(T_912, UInt<2>(3), T_1219)
-    node T_1221 = mux(T_910, UInt<2>(3), T_1220)
-    node T_1222 = mux(T_908, UInt<2>(3), T_1221)
-    node T_1223 = mux(T_906, UInt<2>(3), T_1222)
-    node T_1224 = mux(T_904, UInt<2>(3), T_1223)
-    node T_1225 = mux(T_902, UInt<2>(3), T_1224)
-    node T_1226 = mux(T_900, UInt<2>(3), T_1225)
-    node T_1227 = mux(T_898, UInt<2>(3), T_1226)
-    node T_1228 = mux(T_896, UInt<2>(3), T_1227)
-    node T_1229 = mux(T_894, UInt<2>(3), T_1228)
-    node T_1230 = mux(T_892, UInt<2>(3), T_1229)
-    node T_1231 = mux(T_890, UInt<2>(3), T_1230)
-    node T_1232 = mux(T_888, UInt<2>(3), T_1231)
-    node T_1233 = mux(T_886, UInt<2>(3), T_1232)
-    node T_1234 = mux(T_884, UInt<2>(3), T_1233)
-    node T_1235 = mux(T_882, UInt<2>(3), T_1234)
-    node T_1236 = mux(T_880, UInt<2>(3), T_1235)
-    node T_1237 = mux(T_878, UInt<2>(3), T_1236)
-    node T_1238 = mux(T_876, UInt<2>(3), T_1237)
-    node T_1239 = mux(T_874, UInt<2>(3), T_1238)
-    node T_1240 = mux(T_872, UInt<2>(3), T_1239)
-    node T_1241 = mux(T_870, UInt<2>(3), T_1240)
-    node T_1242 = mux(T_868, UInt<2>(3), T_1241)
-    node T_1243 = mux(T_866, UInt<2>(0), T_1242)
-    node T_1244 = mux(T_864, UInt<2>(1), T_1243)
-    node T_1245 = mux(T_862, UInt<2>(2), T_1244)
-    node T_1246 = mux(T_860, UInt<2>(3), T_1245)
-    node T_1247 = mux(T_858, UInt<2>(3), T_1246)
-    node T_1248 = mux(T_856, UInt<2>(3), T_1247)
-    node T_1249 = mux(T_854, UInt<2>(3), T_1248)
-    node T_1250 = mux(T_852, UInt<2>(3), T_1249)
-    node T_1251 = mux(T_850, UInt<2>(3), T_1250)
-    node T_1252 = mux(T_848, UInt<2>(3), T_1251)
-    node T_1253 = mux(T_846, UInt<2>(3), T_1252)
-    node T_1254 = mux(T_844, UInt<2>(3), T_1253)
-    node T_1255 = mux(T_842, UInt<2>(3), T_1254)
-    node T_1256 = mux(T_840, UInt<2>(3), T_1255)
-    node T_1257 = mux(T_838, UInt<2>(3), T_1256)
-    node T_1258 = mux(T_836, UInt<2>(3), T_1257)
-    node T_1259 = mux(T_834, UInt<2>(3), T_1258)
-    node T_1260 = mux(T_832, UInt<2>(3), T_1259)
-    node T_1261 = mux(T_916, UInt<3>(7), UInt<3>(7))
-    node T_1262 = mux(T_914, UInt<3>(7), T_1261)
-    node T_1263 = mux(T_912, UInt<3>(7), T_1262)
-    node T_1264 = mux(T_910, UInt<3>(7), T_1263)
-    node T_1265 = mux(T_908, UInt<3>(7), T_1264)
-    node T_1266 = mux(T_906, UInt<3>(7), T_1265)
-    node T_1267 = mux(T_904, UInt<3>(7), T_1266)
-    node T_1268 = mux(T_902, UInt<3>(7), T_1267)
-    node T_1269 = mux(T_900, UInt<3>(7), T_1268)
-    node T_1270 = mux(T_898, UInt<3>(7), T_1269)
-    node T_1271 = mux(T_896, UInt<3>(7), T_1270)
-    node T_1272 = mux(T_894, UInt<3>(7), T_1271)
-    node T_1273 = mux(T_892, UInt<3>(7), T_1272)
-    node T_1274 = mux(T_890, UInt<3>(7), T_1273)
-    node T_1275 = mux(T_888, UInt<3>(7), T_1274)
-    node T_1276 = mux(T_886, UInt<3>(7), T_1275)
-    node T_1277 = mux(T_884, UInt<3>(7), T_1276)
-    node T_1278 = mux(T_882, UInt<3>(7), T_1277)
-    node T_1279 = mux(T_880, UInt<3>(7), T_1278)
-    node T_1280 = mux(T_878, UInt<3>(7), T_1279)
-    node T_1281 = mux(T_876, UInt<3>(7), T_1280)
-    node T_1282 = mux(T_874, UInt<3>(7), T_1281)
-    node T_1283 = mux(T_872, UInt<3>(7), T_1282)
-    node T_1284 = mux(T_870, UInt<3>(7), T_1283)
-    node T_1285 = mux(T_868, UInt<3>(7), T_1284)
-    node T_1286 = mux(T_866, UInt<3>(7), T_1285)
-    node T_1287 = mux(T_864, UInt<3>(7), T_1286)
-    node T_1288 = mux(T_862, UInt<3>(7), T_1287)
-    node T_1289 = mux(T_860, UInt<3>(3), T_1288)
-    node T_1290 = mux(T_858, UInt<3>(4), T_1289)
-    node T_1291 = mux(T_856, UInt<3>(0), T_1290)
-    node T_1292 = mux(T_854, UInt<3>(1), T_1291)
-    node T_1293 = mux(T_852, UInt<3>(2), T_1292)
-    node T_1294 = mux(T_850, UInt<3>(7), T_1293)
-    node T_1295 = mux(T_848, UInt<3>(7), T_1294)
-    node T_1296 = mux(T_846, UInt<3>(7), T_1295)
-    node T_1297 = mux(T_844, UInt<3>(7), T_1296)
-    node T_1298 = mux(T_842, UInt<3>(7), T_1297)
-    node T_1299 = mux(T_840, UInt<3>(7), T_1298)
-    node T_1300 = mux(T_838, UInt<3>(7), T_1299)
-    node T_1301 = mux(T_836, UInt<3>(7), T_1300)
-    node T_1302 = mux(T_834, UInt<3>(7), T_1301)
-    node T_1303 = mux(T_832, UInt<3>(7), T_1302)
-    node T_1304 = mux(T_916, UInt<2>(3), UInt<2>(0))
-    node T_1305 = mux(T_914, UInt<2>(3), T_1304)
-    node T_1306 = mux(T_912, UInt<2>(3), T_1305)
-    node T_1307 = mux(T_910, UInt<2>(3), T_1306)
-    node T_1308 = mux(T_908, UInt<2>(3), T_1307)
-    node T_1309 = mux(T_906, UInt<2>(3), T_1308)
-    node T_1310 = mux(T_904, UInt<2>(0), T_1309)
-    node T_1311 = mux(T_902, UInt<2>(0), T_1310)
-    node T_1312 = mux(T_900, UInt<2>(0), T_1311)
-    node T_1313 = mux(T_898, UInt<2>(0), T_1312)
-    node T_1314 = mux(T_896, UInt<2>(0), T_1313)
-    node T_1315 = mux(T_894, UInt<2>(0), T_1314)
-    node T_1316 = mux(T_892, UInt<2>(0), T_1315)
-    node T_1317 = mux(T_890, UInt<2>(0), T_1316)
-    node T_1318 = mux(T_888, UInt<2>(0), T_1317)
-    node T_1319 = mux(T_886, UInt<2>(0), T_1318)
-    node T_1320 = mux(T_884, UInt<2>(0), T_1319)
-    node T_1321 = mux(T_882, UInt<2>(0), T_1320)
-    node T_1322 = mux(T_880, UInt<2>(0), T_1321)
-    node T_1323 = mux(T_878, UInt<2>(0), T_1322)
-    node T_1324 = mux(T_876, UInt<2>(0), T_1323)
-    node T_1325 = mux(T_874, UInt<2>(0), T_1324)
-    node T_1326 = mux(T_872, UInt<2>(0), T_1325)
-    node T_1327 = mux(T_870, UInt<2>(0), T_1326)
-    node T_1328 = mux(T_868, UInt<2>(0), T_1327)
-    node T_1329 = mux(T_866, UInt<2>(0), T_1328)
-    node T_1330 = mux(T_864, UInt<2>(0), T_1329)
-    node T_1331 = mux(T_862, UInt<2>(0), T_1330)
-    node T_1332 = mux(T_860, UInt<2>(1), T_1331)
-    node T_1333 = mux(T_858, UInt<2>(1), T_1332)
-    node T_1334 = mux(T_856, UInt<2>(1), T_1333)
-    node T_1335 = mux(T_854, UInt<2>(1), T_1334)
-    node T_1336 = mux(T_852, UInt<2>(1), T_1335)
-    node T_1337 = mux(T_850, UInt<2>(0), T_1336)
-    node T_1338 = mux(T_848, UInt<2>(0), T_1337)
-    node T_1339 = mux(T_846, UInt<2>(0), T_1338)
-    node T_1340 = mux(T_844, UInt<2>(0), T_1339)
-    node T_1341 = mux(T_842, UInt<2>(0), T_1340)
-    node T_1342 = mux(T_840, UInt<2>(0), T_1341)
-    node T_1343 = mux(T_838, UInt<2>(2), T_1342)
-    node T_1344 = mux(T_836, UInt<2>(2), T_1343)
-    node T_1345 = mux(T_834, UInt<2>(0), T_1344)
-    node T_1346 = mux(T_832, UInt<2>(0), T_1345)
-    node T_1347 = mux(T_916, UInt<1>(0), UInt<1>(0))
-    node T_1348 = mux(T_914, UInt<1>(0), T_1347)
-    node T_1349 = mux(T_912, UInt<1>(0), T_1348)
-    node T_1350 = mux(T_910, UInt<1>(0), T_1349)
-    node T_1351 = mux(T_908, UInt<1>(0), T_1350)
-    node T_1352 = mux(T_906, UInt<1>(0), T_1351)
-    node T_1353 = mux(T_904, UInt<1>(1), T_1352)
-    node T_1354 = mux(T_902, UInt<1>(1), T_1353)
-    node T_1355 = mux(T_900, UInt<1>(1), T_1354)
-    node T_1356 = mux(T_898, UInt<1>(1), T_1355)
-    node T_1357 = mux(T_896, UInt<1>(1), T_1356)
-    node T_1358 = mux(T_894, UInt<1>(1), T_1357)
-    node T_1359 = mux(T_892, UInt<1>(1), T_1358)
-    node T_1360 = mux(T_890, UInt<1>(1), T_1359)
-    node T_1361 = mux(T_888, UInt<1>(1), T_1360)
-    node T_1362 = mux(T_886, UInt<1>(1), T_1361)
-    node T_1363 = mux(T_884, UInt<1>(1), T_1362)
-    node T_1364 = mux(T_882, UInt<1>(1), T_1363)
-    node T_1365 = mux(T_880, UInt<1>(1), T_1364)
-    node T_1366 = mux(T_878, UInt<1>(1), T_1365)
-    node T_1367 = mux(T_876, UInt<1>(1), T_1366)
-    node T_1368 = mux(T_874, UInt<1>(1), T_1367)
-    node T_1369 = mux(T_872, UInt<1>(1), T_1368)
-    node T_1370 = mux(T_870, UInt<1>(1), T_1369)
-    node T_1371 = mux(T_868, UInt<1>(1), T_1370)
-    node T_1372 = mux(T_866, UInt<1>(0), T_1371)
-    node T_1373 = mux(T_864, UInt<1>(0), T_1372)
-    node T_1374 = mux(T_862, UInt<1>(0), T_1373)
-    node T_1375 = mux(T_860, UInt<1>(1), T_1374)
-    node T_1376 = mux(T_858, UInt<1>(1), T_1375)
-    node T_1377 = mux(T_856, UInt<1>(1), T_1376)
-    node T_1378 = mux(T_854, UInt<1>(1), T_1377)
-    node T_1379 = mux(T_852, UInt<1>(1), T_1378)
-    node T_1380 = mux(T_850, UInt<1>(0), T_1379)
-    node T_1381 = mux(T_848, UInt<1>(0), T_1380)
-    node T_1382 = mux(T_846, UInt<1>(0), T_1381)
-    node T_1383 = mux(T_844, UInt<1>(0), T_1382)
-    node T_1384 = mux(T_842, UInt<1>(0), T_1383)
-    node T_1385 = mux(T_840, UInt<1>(0), T_1384)
-    node T_1386 = mux(T_838, UInt<1>(1), T_1385)
-    node T_1387 = mux(T_836, UInt<1>(1), T_1386)
-    node T_1388 = mux(T_834, UInt<1>(1), T_1387)
-    node T_1389 = mux(T_832, UInt<1>(1), T_1388)
-    node T_1390 = mux(T_916, UInt<2>(3), UInt<2>(0))
-    node T_1391 = mux(T_914, UInt<2>(2), T_1390)
-    node T_1392 = mux(T_912, UInt<2>(1), T_1391)
-    node T_1393 = mux(T_910, UInt<2>(3), T_1392)
-    node T_1394 = mux(T_908, UInt<2>(2), T_1393)
-    node T_1395 = mux(T_906, UInt<2>(1), T_1394)
-    node T_1396 = mux(T_904, UInt<2>(0), T_1395)
-    node T_1397 = mux(T_902, UInt<2>(0), T_1396)
-    node T_1398 = mux(T_900, UInt<2>(0), T_1397)
-    node T_1399 = mux(T_898, UInt<2>(0), T_1398)
-    node T_1400 = mux(T_896, UInt<2>(0), T_1399)
-    node T_1401 = mux(T_894, UInt<2>(0), T_1400)
-    node T_1402 = mux(T_892, UInt<2>(0), T_1401)
-    node T_1403 = mux(T_890, UInt<2>(0), T_1402)
-    node T_1404 = mux(T_888, UInt<2>(0), T_1403)
-    node T_1405 = mux(T_886, UInt<2>(0), T_1404)
-    node T_1406 = mux(T_884, UInt<2>(0), T_1405)
-    node T_1407 = mux(T_882, UInt<2>(0), T_1406)
-    node T_1408 = mux(T_880, UInt<2>(0), T_1407)
-    node T_1409 = mux(T_878, UInt<2>(0), T_1408)
-    node T_1410 = mux(T_876, UInt<2>(0), T_1409)
-    node T_1411 = mux(T_874, UInt<2>(0), T_1410)
-    node T_1412 = mux(T_872, UInt<2>(0), T_1411)
-    node T_1413 = mux(T_870, UInt<2>(0), T_1412)
-    node T_1414 = mux(T_868, UInt<2>(0), T_1413)
-    node T_1415 = mux(T_866, UInt<2>(0), T_1414)
-    node T_1416 = mux(T_864, UInt<2>(0), T_1415)
-    node T_1417 = mux(T_862, UInt<2>(0), T_1416)
-    node T_1418 = mux(T_860, UInt<2>(0), T_1417)
-    node T_1419 = mux(T_858, UInt<2>(0), T_1418)
-    node T_1420 = mux(T_856, UInt<2>(0), T_1419)
-    node T_1421 = mux(T_854, UInt<2>(0), T_1420)
-    node T_1422 = mux(T_852, UInt<2>(0), T_1421)
-    node T_1423 = mux(T_850, UInt<2>(0), T_1422)
-    node T_1424 = mux(T_848, UInt<2>(0), T_1423)
-    node T_1425 = mux(T_846, UInt<2>(0), T_1424)
-    node T_1426 = mux(T_844, UInt<2>(0), T_1425)
-    node T_1427 = mux(T_842, UInt<2>(0), T_1426)
-    node T_1428 = mux(T_840, UInt<2>(0), T_1427)
-    node T_1429 = mux(T_838, UInt<2>(0), T_1428)
-    node T_1430 = mux(T_836, UInt<2>(0), T_1429)
-    node T_1431 = mux(T_834, UInt<2>(0), T_1430)
-    node T_1432 = mux(T_832, UInt<2>(0), T_1431)
-    node rs1_addr = bits(ctrl.inst, 19, 15)
-    node rs2_addr = bits(ctrl.inst, 24, 20)
-    reg st_type : UInt<2>
-    reg ld_type : UInt<3>
-    reg wb_sel : UInt<2>
-    node T_1433 = bit(T_1389, 0)
-    reg wb_en : UInt<1>
-    reg csr_cmd : UInt<2>
-    ctrl.pc_sel := T_959
-    node T_1434 = bit-not(ctrl.stall)
-    node T_1435 = bit-not(ctrl.data_re)
-    node T_1436 = bit-and(T_1434, T_1435)
-    ctrl.inst_re := T_1436
-    node T_1437 = neq(T_1303, UInt<3>(7))
-    node T_1438 = bit(T_1217, 0)
-    node T_1439 = bit-or(T_1437, T_1438)
-    node T_1440 = mux(T_1439, UInt<1>(1), UInt<1>(0))
-    ctrl.inst_type := T_1440
-    ctrl.A_sel := T_1002
-    ctrl.B_sel := T_1045
-    ctrl.imm_sel := T_1088
-    ctrl.alu_op := T_1131
-    ctrl.br_type := T_1174
-    ctrl.st_type := T_1260
-    node T_1441 = bit-not(ctrl.stall)
-    when T_1441 : 
-      st_type := ctrl.st_type
-      ld_type := T_1303
-      wb_sel := T_1346
-      node T_1442 = bit(T_1389, 0)
-      wb_en := T_1442
-      csr_cmd := T_1432
-    node T_1443 = neq(ctrl.ld_type, UInt<3>(7))
-    node T_1444 = neq(T_1303, UInt<3>(7))
-    node T_1445 = mux(ctrl.stall, T_1443, T_1444)
-    ctrl.data_re := T_1445
-    ctrl.ld_type := ld_type
-    ctrl.wb_en := wb_en
-    ctrl.wb_sel := wb_sel
-    ctrl.csr_cmd := csr_cmd
diff --git a/test/passes/jacktest/Datapath.fir b/test/passes/jacktest/Datapath.fir
deleted file mode 100644
index abb902ba..00000000
--- a/test/passes/jacktest/Datapath.fir
+++ /dev/null
@@ -1,364 +0,0 @@
-; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s
-;CHECK: Done!
-circuit Datapath : 
-  module ALU : 
-    input B : UInt<32>
-    output out : UInt<32>
-    output sum : UInt<32>
-    input A : UInt<32>
-    input alu_op : UInt<4>
-    
-    node shamt = bits(B, 4, 0)
-    node T_433 = add-wrap(A, B)
-    node T_434 = sub-wrap(A, B)
-    node T_435 = convert(A)
-    node T_436 = dshr(T_435, shamt)
-    node T_437 = as-UInt(T_436)
-    node T_438 = dshr(A, shamt)
-    node T_439 = dshl(A, shamt)
-    node T_440 = bits(T_439, 31, 0)
-    node T_441 = convert(A)
-    node T_442 = convert(B)
-    node T_443 = lt(T_441, T_442)
-    node T_444 = as-UInt(T_443)
-    node T_445 = lt(A, B)
-    node T_446 = as-UInt(T_445)
-    node T_447 = bit-and(A, B)
-    node T_448 = bit-or(A, B)
-    node T_449 = bit-xor(A, B)
-    node T_450 = eq(UInt<4>(10), alu_op)
-    node T_451 = mux(T_450, A, B)
-    node T_452 = eq(UInt<4>(4), alu_op)
-    node T_453 = mux(T_452, T_449, T_451)
-    node T_454 = eq(UInt<4>(3), alu_op)
-    node T_455 = mux(T_454, T_448, T_453)
-    node T_456 = eq(UInt<4>(2), alu_op)
-    node T_457 = mux(T_456, T_447, T_455)
-    node T_458 = eq(UInt<4>(7), alu_op)
-    node T_459 = mux(T_458, T_446, T_457)
-    node T_460 = eq(UInt<4>(5), alu_op)
-    node T_461 = mux(T_460, T_444, T_459)
-    node T_462 = eq(UInt<4>(6), alu_op)
-    node T_463 = mux(T_462, T_440, T_461)
-    node T_464 = eq(UInt<4>(8), alu_op)
-    node T_465 = mux(T_464, T_438, T_463)
-    node T_466 = eq(UInt<4>(9), alu_op)
-    node T_467 = mux(T_466, T_437, T_465)
-    node T_468 = eq(UInt<4>(1), alu_op)
-    node T_469 = mux(T_468, T_434, T_467)
-    node T_470 = eq(UInt<4>(0), alu_op)
-    node oot = mux(T_470, T_433, T_469)
-    node T_471 = bits(oot, 31, 0)
-    out := T_471
-    node T_472 = bit(alu_op, 0)
-    node T_473 = sub-wrap(UInt<1>(0), B)
-    node T_474 = mux(T_472, T_473, B)
-    node T_475 = add-wrap(A, T_474)
-    sum := T_475
-  module BrCond : 
-    input br_type : UInt<3>
-    output taken : UInt<1>
-    input rs2 : UInt<32>
-    input rs1 : UInt<32>
-    
-    node eq = eq(rs1, rs2)
-    node neq = bit-not(eq)
-    node T_476 = convert(rs1)
-    node T_477 = convert(rs2)
-    node lt = lt(T_476, T_477)
-    node ge = bit-not(lt)
-    node ltu = lt(rs1, rs2)
-    node geu = bit-not(ltu)
-    node T_478 = eq(br_type, UInt<3>(2))
-    node T_479 = bit-and(T_478, eq)
-    node T_480 = eq(br_type, UInt<3>(6))
-    node T_481 = bit-and(T_480, neq)
-    node T_482 = bit-or(T_479, T_481)
-    node T_483 = eq(br_type, UInt<3>(1))
-    node T_484 = bit-and(T_483, lt)
-    node T_485 = bit-or(T_482, T_484)
-    node T_486 = eq(br_type, UInt<3>(5))
-    node T_487 = bit-and(T_486, ge)
-    node T_488 = bit-or(T_485, T_487)
-    node T_489 = eq(br_type, UInt<3>(0))
-    node T_490 = bit-and(T_489, ltu)
-    node T_491 = bit-or(T_488, T_490)
-    node T_492 = eq(br_type, UInt<3>(4))
-    node T_493 = bit-and(T_492, geu)
-    node T_494 = bit-or(T_491, T_493)
-    taken := T_494
-  module RegFile : 
-    input waddr : UInt<5>
-    input wdata : UInt<32>
-    input raddr1 : UInt<5>
-    input raddr2 : UInt<5>
-    output rdata2 : UInt<32>
-    output rdata1 : UInt<32>
-    input wen : UInt<1>
-    
-    mem regs : UInt<32>[32]
-    node T_495 = eq(raddr1, UInt<1>(0))
-    node T_496 = bit-not(T_495)
-    accessor T_497 = regs[raddr1]
-    node T_498 = mux(T_496, T_497, UInt<1>(0))
-    rdata1 := T_498
-    node T_499 = eq(raddr2, UInt<1>(0))
-    node T_500 = bit-not(T_499)
-    accessor T_501 = regs[raddr2]
-    node T_502 = mux(T_500, T_501, UInt<1>(0))
-    rdata2 := T_502
-    node T_503 = eq(waddr, UInt<1>(0))
-    node T_504 = bit-not(T_503)
-    node T_505 = bit-and(wen, T_504)
-    when T_505 : 
-      accessor T_506 = regs[waddr]
-      T_506 := wdata
-  module ImmGenWire : 
-    output out : UInt<32>
-    input inst : UInt<32>
-    input sel : UInt<3>
-    
-    node T_507 = bits(inst, 31, 20)
-    node Iimm = convert(T_507)
-    node T_508 = bits(inst, 31, 25)
-    node T_509 = bits(inst, 11, 7)
-    node T_510 = cat(T_508, T_509)
-    node Simm = convert(T_510)
-    node T_511 = bit(inst, 31)
-    node T_512 = bit(inst, 7)
-    node T_513 = bits(inst, 30, 25)
-    node T_514 = bits(inst, 11, 8)
-    node T_515 = cat(T_511, T_512)
-    node T_516 = cat(T_514, UInt<1>(0))
-    node T_517 = cat(T_513, T_516)
-    node T_518 = cat(T_515, T_517)
-    node Bimm = convert(T_518)
-    node T_519 = bits(inst, 31, 12)
-    node T_520 = cat(T_519, UInt<12>(0))
-    node Uimm = convert(T_520)
-    node T_521 = bit(inst, 31)
-    node T_522 = bits(inst, 19, 12)
-    node T_523 = bit(inst, 20)
-    node T_524 = bits(inst, 30, 25)
-    node T_525 = bits(inst, 24, 21)
-    node T_526 = cat(T_522, T_523)
-    node T_527 = cat(T_521, T_526)
-    node T_528 = cat(T_525, UInt<1>(0))
-    node T_529 = cat(T_524, T_528)
-    node T_530 = cat(T_527, T_529)
-    node Jimm = convert(T_530)
-    node T_531 = bits(inst, 19, 15)
-    node T_532 = Pad(T_531, 32)
-    node Zimm = convert(T_532)
-    node T_533 = eq(UInt<3>(3), sel)
-    node T_534 = mux(T_533, Jimm, Zimm)
-    node T_535 = eq(UInt<3>(2), sel)
-    node T_536 = mux(T_535, Uimm, T_534)
-    node T_537 = eq(UInt<3>(4), sel)
-    node T_538 = mux(T_537, Bimm, T_536)
-    node T_539 = eq(UInt<3>(1), sel)
-    node T_540 = mux(T_539, Simm, T_538)
-    node T_541 = eq(UInt<3>(0), sel)
-    node T_542 = mux(T_541, Iimm, T_540)
-    node T_543 = as-UInt(T_542)
-    out := T_543
-  module CSR : 
-    output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>}
-    input src : UInt<32>
-    input cmd : UInt<2>
-    output data : UInt<32>
-    input addr : UInt<12>
-    
-    reg reg_tohost : UInt<32>
-    on-reset reg_tohost := UInt<32>(0)
-    reg reg_status : UInt<32>
-    on-reset reg_status := UInt<32>(0)
-    host.tohost := reg_tohost
-    host.status := reg_status
-    node T_544 = eq(UInt<12>(1291), addr)
-    node T_545 = mux(T_544, host.hid, UInt<1>(0))
-    node T_546 = eq(UInt<12>(1290), addr)
-    node T_547 = mux(T_546, reg_status, T_545)
-    node T_548 = eq(UInt<12>(1310), addr)
-    node T_549 = mux(T_548, reg_tohost, T_547)
-    data := T_549
-    node T_550 = eq(cmd, UInt<2>(1))
-    when T_550 : 
-      node T_551 = eq(addr, UInt<12>(1310))
-      when T_551 : reg_tohost := src
-      node T_552 = eq(addr, UInt<12>(1290))
-      when T_552 : reg_status := src
-    node T_553 = eq(cmd, UInt<2>(2))
-    node T_554 = neq(src, UInt<1>(0))
-    node T_555 = bit-and(T_553, T_554)
-    when T_555 : 
-      node T_556 = eq(addr, UInt<12>(1310))
-      when T_556 : 
-        node T_557 = dshl(UInt<1>(1), src)
-        node T_558 = bit-or(data, T_557)
-        reg_tohost := T_558
-      node T_559 = eq(addr, UInt<12>(1290))
-      when T_559 : 
-        node T_560 = dshl(UInt<1>(1), src)
-        node T_561 = bit-or(data, T_560)
-        reg_status := T_561
-    node T_562 = eq(cmd, UInt<2>(3))
-    node T_563 = neq(src, UInt<1>(0))
-    node T_564 = bit-and(T_562, T_563)
-    when T_564 : 
-      node T_565 = eq(addr, UInt<12>(1310))
-      when T_565 : 
-        node T_566 = dshl(UInt<1>(0), src)
-        node T_567 = bit-and(data, T_566)
-        reg_tohost := T_567
-      node T_568 = eq(addr, UInt<12>(1290))
-      when T_568 : 
-        node T_569 = dshl(UInt<1>(0), src)
-        node T_570 = bit-and(data, T_569)
-        reg_status := T_570
-  module Datapath : 
-    output host : {status : UInt<32>, tohost : UInt<32>, flip hid : UInt<1>}
-    output dcache : {re : UInt<1>, din : UInt<32>, we : UInt<4>, addr : UInt<32>, flip dout : UInt<32>}
-    input stall : UInt<1>
-    output icache : {re : UInt<1>, din : UInt<32>, we : UInt<4>, addr : UInt<32>, flip dout : UInt<32>}
-    input ctrl : {data_re : UInt<1>, ld_type : UInt<3>, flip inst : UInt<32>, br_type : UInt<3>, pc_sel : UInt<1>, wb_sel : UInt<2>, A_sel : UInt<1>, inst_re : UInt<1>, B_sel : UInt<1>, st_type : UInt<2>, alu_op : UInt<4>, csr_cmd : UInt<2>, flip stall : UInt<1>, wb_en : UInt<1>, imm_sel : UInt<3>, inst_type : UInt<1>}
-    
-    inst alu of ALU
-    inst brCond of BrCond
-    inst regFile of RegFile
-    inst immGen of ImmGenWire
-    reg fe_inst : UInt<32>
-    on-reset fe_inst := UInt<32>(0)
-    reg fe_pc : UInt
-    reg ew_inst : UInt<32>
-    on-reset ew_inst := UInt<32>(0)
-    reg ew_pc : UInt
-    reg ew_alu : UInt
-    node T_571 = sub-wrap(UInt<14>(8192), UInt<32>(4))
-    reg pc : UInt<32>
-    on-reset pc := T_571
-    node T_572 = eq(ctrl.pc_sel, UInt<1>(1))
-    node T_573 = bit-or(T_572, brCond.taken)
-    node T_574 = add-wrap(pc, UInt<3>(4))
-    node iaddr = mux(T_573, alu.sum, T_574)
-    node T_575 = eq(ctrl.inst_type, UInt<1>(1))
-    node T_576 = bit-or(T_575, brCond.taken)
-    node inst = mux(T_576, UInt<32>(19), icache.dout)
-    icache.we := UInt<1>(0)
-    icache.din := UInt<1>(0)
-    icache.addr := iaddr
-    icache.re := ctrl.inst_re
-    node T_577 = eq(dcache.we, UInt<1>(0))
-    node T_578 = bit-not(T_577)
-    node T_579 = bit-not(T_578)
-    node T_580 = bit-and(icache.re, T_579)
-    node T_581 = mux(T_580, iaddr, pc)
-    pc := T_581
-    node T_582 = bit-not(stall)
-    when T_582 : 
-      fe_pc := pc
-      fe_inst := inst
-    ctrl.inst := fe_inst
-    ctrl.stall := stall
-    node rd_addr = bits(fe_inst, 11, 7)
-    node rs1_addr = bits(fe_inst, 19, 15)
-    node rs2_addr = bits(fe_inst, 24, 20)
-    regFile.raddr1 := rs1_addr
-    regFile.raddr2 := rs2_addr
-    immGen.inst := fe_inst
-    immGen.sel := ctrl.imm_sel
-    node T_583 = eq(rs1_addr, UInt<1>(0))
-    node rs1NotZero = bit-not(T_583)
-    node T_584 = eq(rs2_addr, UInt<1>(0))
-    node rs2NotZero = bit-not(T_584)
-    node T_585 = eq(ctrl.wb_sel, UInt<2>(0))
-    node alutype = bit-and(ctrl.wb_en, T_585)
-    node ex_rd_addr = bits(ew_inst, 11, 7)
-    node T_586 = bit-and(alutype, rs1NotZero)
-    node T_587 = eq(rs1_addr, ex_rd_addr)
-    node T_588 = bit-and(T_586, T_587)
-    node rs1 = mux(T_588, ew_alu, regFile.rdata1)
-    node T_589 = bit-and(alutype, rs2NotZero)
-    node T_590 = eq(rs2_addr, ex_rd_addr)
-    node T_591 = bit-and(T_589, T_590)
-    node rs2 = mux(T_591, ew_alu, regFile.rdata2)
-    node T_592 = eq(ctrl.A_sel, UInt<1>(0))
-    node T_593 = mux(T_592, rs1, fe_pc)
-    alu.A := T_593
-    node T_594 = eq(ctrl.B_sel, UInt<1>(0))
-    node T_595 = mux(T_594, rs2, immGen.out)
-    alu.B := T_595
-    alu.alu_op := ctrl.alu_op
-    brCond.rs1 := rs1
-    brCond.rs2 := rs2
-    brCond.br_type := ctrl.br_type
-    node T_596 = bit(alu.sum, 1)
-    node T_597 = dshl(T_596, UInt<3>(4))
-    node T_598 = bit(alu.sum, 0)
-    node T_599 = dshl(T_598, UInt<2>(3))
-    node woffset = bit-or(T_597, T_599)
-    dcache.re := ctrl.data_re
-    node T_600 = mux(stall, ew_alu, alu.sum)
-    dcache.addr := T_600
-    node T_601 = bits(alu.sum, 1, 0)
-    node T_602 = dshl(UInt<2>(3), T_601)
-    node T_603 = bits(T_602, 3, 0)
-    node T_604 = bits(alu.sum, 1, 0)
-    node T_605 = dshl(UInt<1>(1), T_604)
-    node T_606 = bits(T_605, 3, 0)
-    node T_607 = eq(UInt<2>(2), ctrl.st_type)
-    node T_608 = mux(T_607, T_606, UInt<4>(0))
-    node T_609 = eq(UInt<2>(1), ctrl.st_type)
-    node T_610 = mux(T_609, T_603, T_608)
-    node T_611 = eq(UInt<2>(0), ctrl.st_type)
-    node T_612 = mux(T_611, UInt<4>(15), T_610)
-    node T_613 = mux(stall, UInt<4>(0), T_612)
-    dcache.we := T_613
-    node T_614 = dshl(rs2, woffset)
-    node T_615 = bits(T_614, 31, 0)
-    dcache.din := T_615
-    node T_616 = bit-not(stall)
-    when T_616 : 
-      ew_pc := fe_pc
-      ew_inst := fe_inst
-      ew_alu := alu.out
-    node T_617 = bit(ew_alu, 1)
-    node T_618 = dshl(T_617, UInt<3>(4))
-    node T_619 = bit(ew_alu, 0)
-    node T_620 = dshl(T_619, UInt<2>(3))
-    node loffset = bit-or(T_618, T_620)
-    node lshift = dshr(dcache.dout, loffset)
-    node T_621 = bits(lshift, 15, 0)
-    node T_622 = convert(T_621)
-    node T_623 = Pad(T_622, 32)
-    node T_624 = as-UInt(T_623)
-    node T_625 = bits(lshift, 7, 0)
-    node T_626 = convert(T_625)
-    node T_627 = Pad(T_626, 32)
-    node T_628 = as-UInt(T_627)
-    node T_629 = bits(lshift, 15, 0)
-    node T_630 = bits(lshift, 7, 0)
-    node T_631 = eq(UInt<3>(4), ctrl.ld_type)
-    node T_632 = mux(T_631, T_630, dcache.dout)
-    node T_633 = eq(UInt<3>(3), ctrl.ld_type)
-    node T_634 = mux(T_633, T_629, T_632)
-    node T_635 = eq(UInt<3>(2), ctrl.ld_type)
-    node T_636 = mux(T_635, T_628, T_634)
-    node T_637 = eq(UInt<3>(1), ctrl.ld_type)
-    node load = mux(T_637, T_624, T_636)
-    inst csr of CSR
-    host := csr.host
-    csr.src := ew_alu
-    node T_638 = bits(ew_inst, 31, 20)
-    csr.addr := T_638
-    csr.cmd := ctrl.csr_cmd
-    node T_639 = add-wrap(ew_pc, UInt<3>(4))
-    node T_640 = eq(UInt<2>(3), ctrl.wb_sel)
-    node T_641 = mux(T_640, csr.data, ew_alu)
-    node T_642 = eq(UInt<2>(2), ctrl.wb_sel)
-    node T_643 = mux(T_642, T_639, T_641)
-    node T_644 = eq(UInt<2>(1), ctrl.wb_sel)
-    node regWrite = mux(T_644, load, T_643)
-    regFile.wen := ctrl.wb_en
-    regFile.waddr := ex_rd_addr
-    regFile.wdata := regWrite
diff --git a/test/passes/jacktest/Stack.fir b/test/passes/jacktest/Stack.fir
index d42e1dd5..43f61827 100644
--- a/test/passes/jacktest/Stack.fir
+++ b/test/passes/jacktest/Stack.fir
@@ -8,7 +8,7 @@ circuit Stack :
     output dataOut : UInt<32>
     input dataIn : UInt<32>
     
-    mem stack_mem : UInt<32>[16]
+    cmem stack_mem : UInt<32>[16]
     reg sp : UInt<5>
     on-reset sp := UInt<5>(0)
     reg out : UInt<32>
diff --git a/test/passes/jacktest/Tbl.fir b/test/passes/jacktest/Tbl.fir
index bf7635fb..4e0e954c 100644
--- a/test/passes/jacktest/Tbl.fir
+++ b/test/passes/jacktest/Tbl.fir
@@ -7,7 +7,7 @@ circuit Tbl :
     output o : UInt<16>
     input we : UInt<1>
     
-    mem m : UInt<10>[256]
+    cmem m : UInt<10>[256]
     o := UInt<1>(0)
     when we : 
       accessor T_13 = m[i]
diff --git a/test/passes/jacktest/risc.fir b/test/passes/jacktest/risc.fir
index 875498d6..4d02bcf7 100644
--- a/test/passes/jacktest/risc.fir
+++ b/test/passes/jacktest/risc.fir
@@ -9,8 +9,8 @@ circuit Risc :
     input wrAddr : UInt<8>
     input wrData : UInt<32>
     
-    mem file : UInt<32>[256]
-    mem code : UInt<32>[256]
+    cmem file : UInt<32>[256]
+    cmem code : UInt<32>[256]
     reg pc : UInt<8>
     on-reset pc := UInt<8>(0)
     accessor inst = code[pc]
diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir
index 14b55c63..8fe1bc52 100644
--- a/test/passes/lower-to-ground/accessor.fir
+++ b/test/passes/lower-to-ground/accessor.fir
@@ -7,22 +7,22 @@ circuit top :
       wire j : UInt<32>
 
       wire a : UInt<32>[4]
-      ; CHECK: wire a_0 : UInt<32>
-      ; CHECK: wire a_1 : UInt<32>
-      ; CHECK: wire a_2 : UInt<32>
-      ; CHECK: wire a_3 : UInt<32>
+      ; CHECK: wire a$0 : UInt<32>
+      ; CHECK: wire a$1 : UInt<32>
+      ; CHECK: wire a$2 : UInt<32>
+      ; CHECK: wire a$3 : UInt<32>
 
       accessor b = a[i]
       ; CHECK: wire b : UInt<32>
-      ; CHECK: b := (a_0 a_1 a_2 a_3)[i]
+      ; CHECK: b := (a$0 a$1 a$2 a$3)[i]
       j := b
 
       accessor c = a[i]
       ; CHECK: wire c : UInt<32>
-      ; CHECK: (a_0 a_1 a_2 a_3)[i] := c
+      ; CHECK: (a$0 a$1 a$2 a$3)[i] := c
       c := j
       
-      mem p : UInt<32>[4]
+      cmem p : UInt<32>[4]
       accessor t = p[i]
       ; CHECK: accessor t = p[i]
       j := t
diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir
index 069314a3..0b9d9799 100644
--- a/test/passes/lower-to-ground/bundle-vecs.fir
+++ b/test/passes/lower-to-ground/bundle-vecs.fir
@@ -7,23 +7,23 @@ circuit top :
       wire j : { x : UInt<32>, flip y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
-      ; CHECK: wire a_0_x : UInt<32>
-      ; CHECK: wire a_0_y : UInt<32>
-      ; CHECK: wire a_1_x : UInt<32>
-      ; CHECK: wire a_1_y : UInt<32>
+      ; CHECK: wire a$0$x : UInt<32>
+      ; CHECK: wire a$0$y : UInt<32>
+      ; CHECK: wire a$1$x : UInt<32>
+      ; CHECK: wire a$1$y : UInt<32>
 
       accessor b = a[i]
-      ; CHECK: wire b_x : UInt<32>
-      ; CHECK: wire b_y : UInt<32>
-      ; CHECK: b_x := (a_0_x a_1_x)[i]
-      ; CHECK: (a_0_y a_1_y)[i] := b_y
+      ; CHECK: wire b$x : UInt<32>
+      ; CHECK: wire b$y : UInt<32>
+      ; CHECK: b$x := (a$0$x a$1$x)[i]
+      ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
       
       accessor c = a[i]
-      ; CHECK: wire c_x : UInt<32>
-      ; CHECK: wire c_y : UInt<32>
-      ; CHECK: (a_0_x a_1_x)[i] := c_x
-      ; CHECK: c_y := (a_0_y a_1_y)[i]
+      ; CHECK: wire c$x : UInt<32>
+      ; CHECK: wire c$y : UInt<32>
+      ; CHECK: (a$0$x a$1$x)[i] := c$x
+      ; CHECK: c$y := (a$0$y a$1$y)[i]
       c := j
 
 
diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir
index e758acaf..c0acfecd 100644
--- a/test/passes/lower-to-ground/bundle.fir
+++ b/test/passes/lower-to-ground/bundle.fir
@@ -17,37 +17,37 @@ circuit top :
 ;CHECK: Lower To Ground
 ;CHECK: circuit top :
 ;CHECK:    module m :
-;CHECK:       input a_x : UInt<5>
-;CHECK:       output a_y : SInt<5>
-;CHECK:       output b_x : UInt<5>
-;CHECK:       input b_y : SInt<5>
+;CHECK:       input a$x : UInt<5>
+;CHECK:       output a$y : SInt<5>
+;CHECK:       output b$x : UInt<5>
+;CHECK:       input b$y : SInt<5>
 ;CHECK:       input reset : UInt<1>
 ;CHECK:    module top :
-;CHECK:       input c_x_0 : UInt<5>
-;CHECK:       input c_x_1 : UInt<5>
-;CHECK:       input c_x_2 : UInt<5>
-;CHECK:       input c_x_3 : UInt<5>
-;CHECK:       input c_x_4 : UInt<5>
-;CHECK:       output c_y_x_0 : UInt<5>
-;CHECK:       output c_y_x_1 : UInt<5>
-;CHECK:       output c_y_x_2 : UInt<5>
-;CHECK:       input c_y_y : SInt<5>
+;CHECK:       input c$x$0 : UInt<5>
+;CHECK:       input c$x$1 : UInt<5>
+;CHECK:       input c$x$2 : UInt<5>
+;CHECK:       input c$x$3 : UInt<5>
+;CHECK:       input c$x$4 : UInt<5>
+;CHECK:       output c$y$x$0 : UInt<5>
+;CHECK:       output c$y$x$1 : UInt<5>
+;CHECK:       output c$y$x$2 : UInt<5>
+;CHECK:       input c$y$y : SInt<5>
 ;CHECK:       input reset : UInt<1>
-;CHECK:       wire a_x : UInt<5>
-;CHECK:       wire a_y : SInt<5>
-;CHECK:       wire b_x : UInt<5>
-;CHECK:       wire b_y : SInt<5>
-;CHECK:       a_x := b_x
-;CHECK:       b_y := a_y
+;CHECK:       wire a$x : UInt<5>
+;CHECK:       wire a$y : SInt<5>
+;CHECK:       wire b$x : UInt<5>
+;CHECK:       wire b$y : SInt<5>
+;CHECK:       a$x := b$x
+;CHECK:       b$y := a$y
 ;CHECK:       inst i of m
 ;CHECK:       i.reset := reset
-;CHECK:       i.a_x := a_x
-;CHECK:       a_y := i.a_y
-;CHECK:       b_x := i.b_x
-;CHECK:       i.b_y := b_y
-;CHECK:       wire d_0 : UInt<5>
-;CHECK:       wire d_1 : UInt<5>
-;CHECK:       wire d_2 : UInt<5>
-;CHECK:       wire d_3 : UInt<5>
-;CHECK:       wire d_4 : UInt<5>
+;CHECK:       i.a$x := a$x
+;CHECK:       a$y := i.a$y
+;CHECK:       b$x := i.b$x
+;CHECK:       i.b$y := b$y
+;CHECK:       wire d$0 : UInt<5>
+;CHECK:       wire d$1 : UInt<5>
+;CHECK:       wire d$2 : UInt<5>
+;CHECK:       wire d$3 : UInt<5>
+;CHECK:       wire d$4 : UInt<5>
 ;CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir
index 57c68398..420c3c7c 100644
--- a/test/passes/lower-to-ground/instance.fir
+++ b/test/passes/lower-to-ground/instance.fir
@@ -27,9 +27,9 @@ circuit top :
 
 ; CHECK: Lower To Ground
 
-; CHECK: connect_data@<g:f> := src@<g:m>.data@<g:m>
-; CHECK: src@<g:m>.ready@<g:f> := connect_ready@<g:m>
-; CHECK: snk@<g:m>.data@<g:f> := connect2_data@<g:m>
-; CHECK: connect2_ready@<g:f> := snk@<g:m>.ready@<g:m>
+; CHECK: connect$data@<g:f> := src@<g:m>.data@<g:m>
+; CHECK: src@<g:m>.ready@<g:f> := connect$ready@<g:m>
+; CHECK: snk@<g:m>.data@<g:f> := connect2$data@<g:m>
+; CHECK: connect2$ready@<g:f> := snk@<g:m>.ready@<g:m>
 
 ; CHECK: Finished Lower To Ground
diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir
index 1a6ba2e8..c39850f4 100644
--- a/test/passes/lower-to-ground/nested-vec.fir
+++ b/test/passes/lower-to-ground/nested-vec.fir
@@ -8,29 +8,29 @@ circuit top :
       wire k : { x : UInt<32>, y : UInt<32> }
 
       wire a : { x : UInt<32>, flip y : UInt<32> }[2]
-      ; CHECK: wire a_0_x : UInt<32>
-      ; CHECK: wire a_0_y : UInt<32>
-      ; CHECK: wire a_1_x : UInt<32>
-      ; CHECK: wire a_1_y : UInt<32>
+      ; CHECK: wire a$0$x : UInt<32>
+      ; CHECK: wire a$0$y : UInt<32>
+      ; CHECK: wire a$1$x : UInt<32>
+      ; CHECK: wire a$1$y : UInt<32>
 
       accessor b = a[i]
-      ; CHECK: wire b_x : UInt<32>
-      ; CHECK: wire b_y : UInt<32>
-      ; CHECK: b_x := (a_0_x a_1_x)[i]
-      ; CHECK: (a_0_y a_1_y)[i] := b_y
+      ; CHECK: wire b$x : UInt<32>
+      ; CHECK: wire b$y : UInt<32>
+      ; CHECK: b$x := (a$0$x a$1$x)[i]
+      ; CHECK: (a$0$y a$1$y)[i] := b$y
       j := b
 
-      mem m : { x : UInt<32>, y : UInt<32> }[2]
-      ; CHECK: mem m_x : UInt<32>[2]
-      ; CHECK: mem m_y : UInt<32>[2]
+      cmem m : { x : UInt<32>, y : UInt<32> }[2]
+      ; CHECK: cmem m$x : UInt<32>[2]
+      ; CHECK: cmem m$y : UInt<32>[2]
 
       accessor c = m[i] ; MALE
-      ; CHECK: accessor c_x = m_x[i]
-      ; CHECK: accessor c_y = m_y[i]
+      ; CHECK: accessor c$x = m$x[i]
+      ; CHECK: accessor c$y = m$y[i]
 
       c := k
-      ; CHECK: c_x := k_x
-      ; CHECK: c_y := k_y
+      ; CHECK: c$x := k$x
+      ; CHECK: c$y := k$y
 
 ; CHECK: Finished Lower To Ground
 
diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir
index 449204a3..a3c4f0ae 100644
--- a/test/passes/lower-to-ground/register.fir
+++ b/test/passes/lower-to-ground/register.fir
@@ -11,11 +11,11 @@
                wire q : { x : UInt, flip y : SInt }
                on-reset r1 := q    
 
-      ; CHECK: reg r1_x : UInt
-      ; CHECK: reg r1_y : SInt
-      ; CHECK: wire q_x : UInt
-      ; CHECK: wire q_y : SInt
-      ; CHECK: on-reset r1_x := q_x
-      ; CHECK: on-reset q_y := r1_y   
+      ; CHECK: reg r1$x : UInt
+      ; CHECK: reg r1$y : SInt
+      ; CHECK: wire q$x : UInt
+      ; CHECK: wire q$y : SInt
+      ; CHECK: on-reset r1$x := q$x
+      ; CHECK: on-reset q$y := r1$y   
 
 ; CHECK: Finished Lower To Ground