Fixed bugs in when-coverage pass. Works but has not been thoroughly tested

2 files changed, 36 insertions, 14 deletions

diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza
index d47f6661..e4c3d9d3 100644
--- a/src/main/stanza/custom-passes.stanza
+++ b/src/main/stanza/custom-passes.stanza
@@ -23,7 +23,23 @@ defn concat-all (ls:List<Expression>) -> Expression :
 ;============ When Coverage Pass =============
 ;port width = 1 bit per scope + portwidths of all instances
 
-defn when-coverage (port-name:Symbol, reg-name:Symbol, m:InModule) -> InModule :
+defn needs-instrumentation (m:Module,ms:List<Module>,instrument?:HashTable<Symbol,True|False>) -> False :
+   defn needs-instrumentation-s (s:Stmt) -> False :
+      match(s) :
+         (s:Conditionally) :instrument?[name(m)] = true
+         (s:DefInstance) : 
+            val module-of-inst = for x in ms find : name(x) == name(module(s) as Ref)
+            if module-of-inst != false : 
+               needs-instrumentation(module-of-inst as Module,ms,instrument?)
+               instrument?[name(m)] = instrument?[name(module-of-inst as Module)]
+         (s) : false
+      do(needs-instrumentation-s,s)
+
+   match(m) : 
+      (m:InModule) : do(needs-instrumentation-s,body(m))
+      (m:ExModule) : false
+   
+defn when-coverage (port-name:Symbol, reg-name:Symbol, instrument?:HashTable<Symbol,True|False>, m:InModule) -> InModule :
    val when-bits = Vector<Ref>()
    val inst-bits = Vector<Ref>()
    val sym = HashTable<Symbol,Int>(symbol-hash)
@@ -31,21 +47,24 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, m:InModule) -> InModule :
    val t1 = UIntType(w1)
    val u1 = UIntValue(1,w1)
    defn when-coverage (s:Stmt) -> Stmt :
-      map{when-coverage,_} $ match(s) :
+      match(s) :
          (s:Conditionally) : 
             val ref = Ref(firrtl-gensym(reg-name,sym),t1)
             add(when-bits,ref)
             val conseq* = Begin(list(Connect(FileInfo()ref,u1),conseq(s)))
-            Conditionally(info(s),pred(s),conseq*,alt(s))
+            map(when-coverage,Conditionally(info(s),pred(s),conseq*,alt(s)))
          (s:DefInstance) : 
-            val ref = Ref(firrtl-gensym(port-name,sym),t1)
-            add(inst-bits,ref)
-            val sfld = Subfield(Ref(name(s),UnknownType()),port-name,UnknownType())
-            Begin(list(s,Connect(FileInfo(),ref,sfld)))
-         (s) : s
+            if instrument?[name(module(s) as Ref)] :
+               val ref = Ref(firrtl-gensym(port-name,sym),UIntType(UnknownWidth()))
+               add(inst-bits,ref)
+               val sfld = Subfield(Ref(name(s),UnknownType()),port-name,UnknownType())
+               Begin(list(s,Connect(FileInfo(),ref,sfld)))
+            else : s
+         (s) : map(when-coverage,s)
 
    val body* = when-coverage(body(m))
    val logic = Vector<Stmt>()
+   val port-ref = Ref(port-name,UIntType(UnknownWidth()))
 
    val w-ls = to-list $ when-bits
    if length(w-ls) != 0 :
@@ -59,11 +78,11 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, m:InModule) -> InModule :
 
    val i-ls = to-list $ inst-bits
    if length(i-ls) != 0 :
-      val port-ref = Ref(port-name,UIntType(UnknownWidth()))
       for (x in i-ls, i in 0 to false) do :
          add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
          add{logic,_} $ Connect(FileInfo(),x,UIntValue(0,UnknownWidth()))
-      add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls)))
+
+   if instrument?[name(m)] : add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls)))
 
    if length(logic) != 0 :
       val ports* = List(Port(FileInfo(),port-name,OUTPUT,UIntType(UnknownWidth())),ports(m))
@@ -72,10 +91,16 @@ defn when-coverage (port-name:Symbol, reg-name:Symbol, m:InModule) -> InModule :
    else : m
 
 public defn when-coverage (port-name:String, reg-name:String, c:Circuit) :
+   val instrument? = HashTable<Symbol,True|False>(symbol-hash)
+   for m in modules(c) do :
+      instrument?[name(m)] = false
+   val top = for m in modules(c) find : name(m) == main(c)
+   if top != false : needs-instrumentation(top as Module,modules(c),instrument?)
+
    val modules* = for m in modules(c) map :
       match(m) :
          (m:InModule) : 
-            when-coverage(to-symbol $ port-name,to-symbol $ reg-name,m)
+            when-coverage(to-symbol $ port-name,to-symbol $ reg-name,instrument?,m)
          (m:ExModule) : m
    Circuit(info(c),modules*,main(c))
 
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 1a8f6780..071717bb 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -49,7 +49,6 @@ defn get-passes (pass-names:List<String>) -> List<Pass> :
       p as Pass
          
 defn main () :
-   println("HERE")
    val args = commandline-arguments()
    var input = false
    var output = false
@@ -65,7 +64,6 @@ defn main () :
       if s == "-p" : printvars = args[i + 1]
       if s == "-s" : add(pass-args,args[i + 1])
 
-   println("THERE")
    if input == false : 
       error("No input file provided. Use -i flag.")
    if output == false : 
@@ -77,7 +75,6 @@ defn main () :
    val c = parse-firrtl(lexed)
    set-printvars!(to-list(printvars))
    
-   println("EVERYWHERE")
    if compiler == false :
       run-passes(c,get-passes(to-list(pass-names)))
    else :