| Age | Commit message (Expand) | Author |
|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-02-09 | Added license to FIRRTL files | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asCl... | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-16 | WIP adding chirrtl | azidar |
| 2016-01-16 | WIP Almost there, need to generate enable connections | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2016-01-16 | WIP | azidar |
| 2016-01-16 | Finished adding clocks to Stop and Print | azidar |
| 2015-10-07 | Added Printf and Stop to firrtl. #23 #24. | azidar |
| 2015-10-01 | Changed DefMemory to be a non-vector type with a size member. Necessary for A... | azidar |
| 2015-08-25 | Removed IntWidth, now only use LongWidth. Now do width inference for Constant... | azidar |
| 2015-08-20 | Added Poison node. Includes tests. #26. | azidar |
| 2015-08-19 | Switched to new bigint library | azidar |
| 2015-08-04 | Added check for reading from outputs with flips | azidar |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar |
| 2015-08-03 | Fixed performance bug in Split Expressions. Changed delin for connect indexed... | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-16 | Fixed rename to work with chisel3 stuff | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-29 | Added custom pass. Does not correctly run, stanza just spins. Requires debugg... | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-13 | Added source indicators from FIRRTL files. Pass in -p i to get them printed. ... | azidar |
| 2015-05-05 | Added a bunch of tests. In the middle of implementing check kinds and check t... | azidar |
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar |
| 2015-04-29 | Added dshl and dshr | azidar |
| 2015-04-23 | Not finished commmit | azidar |
| 2015-04-23 | Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc... | azidar |
| 2015-04-22 | Switched to stricter primop width constraints. Implemented Pad. Added some mi... | azidar |
| 2015-04-17 | Fixed bug in primop lowering during type inference. Added reduce instructions... | azidar |
| 2015-04-16 | Merged with new stanza | azidar |
| 2015-04-15 | Finished flo backend. Restructured todo list | azidar |
| 2015-04-10 | Updated Stanza | Patrick Li |
| 2015-04-09 | Added more 'fake' tests. infer-widths now collects constraints | azidar |
| 2015-03-25 | Correctly do when expansion, minus enables and outputting lowered form | azidar |
| 2015-03-24 | Changed PrimOp to interface | Patrick Li |
| 2015-03-23 | Finished first two parts of expand-whens pass. Fixed inits by adding WRegInit... | azidar |
