diff options
| author | Adam Izraelevitz | 2015-07-17 16:49:22 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2015-07-17 16:49:22 -0700 |
| commit | 70567d4d57ac178660fbef0ef660069b52857562 (patch) | |
| tree | ac0ed0127ddb99a72cbc760f6be97b99c574d018 /src/main/stanza/firrtl-ir.stanza | |
| parent | 98bb81d9d99150a80c77ed8f22d44748a02df628 (diff) | |
Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!
Had to separate initialization check pass
Need to write dead code elimination pass
Added LongWidth to support dshl that are huge
Diffstat (limited to 'src/main/stanza/firrtl-ir.stanza')
| -rw-r--r-- | src/main/stanza/firrtl-ir.stanza | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index e57c5f74..15666a9a 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -7,6 +7,7 @@ public defmethod info! (x:?) : FileInfo() public val vector-expand-delin = `$ public val bundle-expand-delin = `$ +public val module-expand-delin = `$ public val scope-delin = `% public val temp-delin = `! public val inline-delin = `^ @@ -29,6 +30,8 @@ public definterface Width public defstruct UnknownWidth <: Width public defstruct IntWidth <: Width : width: Int +public defstruct LongWidth <: Width : + width : Long public definterface PrimOp public val ADD-OP = new PrimOp @@ -174,15 +177,16 @@ public defstruct Port : public definterface Module public defmulti name (m:Module) -> Symbol public defmulti ports (m:Module) -> List<Port> +public defmulti info (m:Module) -> FileInfo public defstruct InModule <: Module : - info: FileInfo + info: FileInfo with: (as-method => true) name: Symbol with: (as-method => true) ports: List<Port> with: (as-method => true) body: Stmt public defstruct ExModule <: Module : - info: FileInfo + info: FileInfo with: (as-method => true) name: Symbol with: (as-method => true) ports: List<Port> with: (as-method => true) |