| Age | Commit message (Expand) | Author |
|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-02-24 | Fixed printf bugs in scala and stanza versions. Required special casing print... | Adam Izraelevitz |
| 2016-02-10 | Re-enable some passes | Palmer Dabbelt |
| 2016-02-09 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2016-02-09 | Added license to FIRRTL files | azidar |
| 2016-02-09 | Added chirrtl passes, need to update parser | azidar |
| 2016-02-09 | More bug fixes | azidar |
| 2016-02-09 | Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of ... | azidar |
| 2016-02-09 | Added Expand Whens pass | azidar |
| 2016-02-09 | Moved check-high-form to operate on working ir | azidar |
| 2016-02-09 | Changed stanza output of UInt/SInt to include widths. Made tests match accord... | azidar |
| 2016-02-09 | Added remove accesses | azidar |
| 2016-02-09 | Added expand connect. Resolve now includes to working ir | azidar |
| 2016-02-09 | WIP. Got to-working-ir working | azidar |
| 2016-02-09 | WIP, nothing works. Starting creating working IR and necessary utils | azidar |
| 2016-02-08 | Escape quotes in strings before emitting as Verilog | Palmer Dabbelt |
| 2016-02-08 | Escape printf argument before emitting them | Palmer Dabbelt |
| 2016-01-28 | Fixed bug where subaccess indexes were being classified as female, | azidar |
| 2016-01-28 | Changed rmode to wmode | azidar |
| 2016-01-28 | Use IsInvalid instead of Poisons in chirrtl -> firrtl transform | azidar |
| 2016-01-28 | Fixed bug where you cannot extract from a single bit wire in verilog. #55. | azidar |
| 2016-01-28 | Fixed bug where needed to cast bit-operation inputs prior to verilog emission | azidar |
| 2016-01-28 | Added addw to working ir as an optimized verilog emission | azidar |
| 2016-01-28 | Add map of symbol->symbol for wdefinstance | azidar |
| 2016-01-28 | Fixed matching on types for and, or, and xor | azidar |
| 2016-01-28 | Fixed bug and updated test for changing mod to rem | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asCl... | azidar |
| 2016-01-28 | Fixed readwriter syntax, and all printed mstats to use => instead of a colon | azidar |
| 2016-01-28 | Changed register syntax for optional reset and init values | azidar |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-27 | Fixed additional tests and inferring rdwr ports in chirrtl | jackkoenig |
| 2016-01-25 | Fixed bug where poisons were not being declared | azidar |
| 2016-01-25 | Added verilog rename pass | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-25 | Removed println in expand when | azidar |
| 2016-01-25 | Fixed width inference bug for muxes | azidar |
| 2016-01-25 | Removed random println | azidar |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar |
| 2016-01-25 | Changed first generated name to use _0 postfix | azidar |
| 2016-01-24 | Made CInfer robust to high firrtl errors | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-24 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-mem | azidar |
| 2016-01-24 | Removed hashing as it made refchip slower to compile | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fix Verilog syntax errors for print/stop | Andrew Waterman |
| 2016-01-23 | Removed buggy optimization of dshr and dshl | azidar |
| 2016-01-23 | Moved inst declarations after other declarations | azidar |
| 2016-01-23 | Fixed commas for instances in verilog | azidar |
| 2016-01-23 | Added more semicolons | azidar |
