Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of rocketchip

2 files changed, 18 insertions, 0 deletions

diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index 0a07fcf0..fc770764 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -11,6 +11,7 @@ public val chirrtl-passes = to-list $ [
    CInferTypes()
    CInferMDir()
    RemoveCHIRRTL()
+   FromCHIRRTL()
 ]
 ; ===============================
 
@@ -421,3 +422,18 @@ defn remove-chirrtl (c:Circuit) :
                (m:ExModule) : m
 
 
+;============ FromCHIRRTL ==============
+
+public defstruct FromCHIRRTL <: Pass
+public defmethod pass (b:FromCHIRRTL) -> (Circuit -> Circuit) : from-chirrtl
+public defmethod name (b:FromCHIRRTL) -> String : "From CHIRRTL"
+public defmethod short-name (b:FromCHIRRTL) -> String : "from-chirrtl"
+
+defn from-chirrtl (c:Circuit) -> Circuit :
+   val c1 = c-infer-types(c)
+   ;println(c1)
+   val c2 = infer-mdir(c1)
+   ;println(c2)
+   val c3 = remove-chirrtl(c2)
+   ;println(c3)
+   c3
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 155c1b0a..9d7a1b97 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2895,3 +2895,5 @@ defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) :
    val c5 = verilog-rename(c4)
    ;println(c5)
    emit-verilog(with-output,c5)
+
+