Added DefMemory to CInfer Types

3 files changed, 41 insertions, 35 deletions

diff --git a/src/main/stanza/chirrtl.stanza b/src/main/stanza/chirrtl.stanza
index 7d6d9d3f..2ac76a05 100644
--- a/src/main/stanza/chirrtl.stanza
+++ b/src/main/stanza/chirrtl.stanza
@@ -114,6 +114,9 @@ defn infer-types (c:Circuit) -> Circuit :
                val t = type(value(s*))
                types[name(s*)] = t
                s*
+            (s:DefMemory) :
+               types[name(s)] = get-type(s)
+               s
             (s:CDefMPort) :
                val t = types[mem(s)]
                types[name(s)] = t
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index fa4b296f..59a4b659 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -157,6 +157,43 @@ public defn swap (f:Flip) -> Flip :
    switch {_ == f} :
       DEFAULT : REVERSE
       REVERSE : DEFAULT
+
+public defmulti get-type (s:Stmt) -> Type
+public defmethod get-type (s:Stmt) -> Type :
+   match(s) :
+      (s:DefWire|DefPoison|DefRegister) : type(s)
+      (s:DefNode) : type(value(s))
+      (s:DefMemory) : 
+         val depth = depth(s)
+         ; Fields
+         val addr = Field(`addr,DEFAULT,UIntType(IntWidth(ceil-log2(depth))))
+         val en = Field(`en,DEFAULT,BoolType())
+         val clk = Field(`clk,DEFAULT,ClockType())
+         val def-data = Field(`data,DEFAULT,data-type(s))
+         val rev-data = Field(`data,REVERSE,data-type(s))
+         val rdata = Field(`rdata,REVERSE,data-type(s))
+         val wdata = Field(`wdata,DEFAULT,data-type(s))
+         val mask = Field(`mask,DEFAULT,create-mask(data-type(s)))
+         val wmask = Field(`wmask,DEFAULT,create-mask(data-type(s)))
+         val ren = Field(`ren,DEFAULT,UIntType(IntWidth(1)))
+         val wen = Field(`wen,DEFAULT,UIntType(IntWidth(1)))
+         val raddr = Field(`raddr,DEFAULT,UIntType(IntWidth(ceil-log2(depth))))
+         val waddr = Field(`waddr,DEFAULT,UIntType(IntWidth(ceil-log2(depth))))
+
+         val read-type = BundleType(to-list([rev-data,addr,en,clk]))
+         val write-type = BundleType(to-list([def-data,mask,addr,en,clk]))
+         val readwrite-type = BundleType(to-list([wdata,wmask,waddr,wen,rdata,raddr,ren,clk]))
+
+         val mem-fields = Vector<Field>()
+         for x in readers(s) do :
+            add(mem-fields,Field(x,DEFAULT,read-type))
+         for x in writers(s) do :
+            add(mem-fields,Field(x,DEFAULT,write-type))
+         for x in readwriters(s) do :
+            add(mem-fields,Field(x,DEFAULT,readwrite-type))
+         BundleType(to-list(mem-fields))
+      (s:DefInstance) : UnknownType()
+      (s:Begin|Connect|BulkConnect|Stop|Print|Empty) : UnknownType()
      
 public defn get-size (t:Type) -> Int :
    val x = match(t) :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index eae4aff2..578af29f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -116,41 +116,7 @@ defmethod info (stmt:Empty) -> FileInfo : FileInfo()
 defmethod type (exp:UIntValue) -> Type : UIntType(width(exp))
 defmethod type (exp:SIntValue) -> Type : SIntType(width(exp))
 
-defn get-type (s:Stmt) -> Type :
-   match(s) :
-      (s:DefWire|DefPoison|DefRegister|WDefInstance) : type(s)
-      (s:DefNode) : type(value(s))
-      (s:DefMemory) : 
-         val depth = depth(s)
-         ; Fields
-         val addr = Field(`addr,DEFAULT,UIntType(IntWidth(ceil-log2(depth))))
-         val en = Field(`en,DEFAULT,BoolType())
-         val clk = Field(`clk,DEFAULT,ClockType())
-         val def-data = Field(`data,DEFAULT,data-type(s))
-         val rev-data = Field(`data,REVERSE,data-type(s))
-         val rdata = Field(`rdata,REVERSE,data-type(s))
-         val wdata = Field(`wdata,DEFAULT,data-type(s))
-         val mask = Field(`mask,DEFAULT,create-mask(data-type(s)))
-         val wmask = Field(`wmask,DEFAULT,create-mask(data-type(s)))
-         val ren = Field(`ren,DEFAULT,UIntType(IntWidth(1)))
-         val wen = Field(`wen,DEFAULT,UIntType(IntWidth(1)))
-         val raddr = Field(`raddr,DEFAULT,UIntType(IntWidth(ceil-log2(depth))))
-         val waddr = Field(`waddr,DEFAULT,UIntType(IntWidth(ceil-log2(depth))))
-
-         val read-type = BundleType(to-list([rev-data,addr,en,clk]))
-         val write-type = BundleType(to-list([def-data,mask,addr,en,clk]))
-         val readwrite-type = BundleType(to-list([wdata,wmask,waddr,wen,rdata,raddr,ren,clk]))
-
-         val mem-fields = Vector<Field>()
-         for x in readers(s) do :
-            add(mem-fields,Field(x,DEFAULT,read-type))
-         for x in writers(s) do :
-            add(mem-fields,Field(x,DEFAULT,write-type))
-         for x in readwriters(s) do :
-            add(mem-fields,Field(x,DEFAULT,readwrite-type))
-         BundleType(to-list(mem-fields))
-      (s:DefInstance) : UnknownType()
-      (s:Begin|Connect|BulkConnect|Stop|Print|Empty) : UnknownType()
+defmethod get-type (s:WDefInstance) -> Type : type(s)
 
 defmethod equal? (e1:Expression,e2:Expression) -> True|False :
    match(e1,e2) :