diff options
| author | azidar | 2016-01-30 13:45:43 -0800 |
|---|---|---|
| committer | azidar | 2016-02-09 18:55:26 -0800 |
| commit | f1b5193353b6e021a0f5e5f33d5ac265f7bc686e (patch) | |
| tree | db8ac0992c95f106dd2553083d01500cd8b80c0f /src/main/stanza | |
| parent | 9e26d71f1131cb086c4ac5cfa05369e40dfb3f1a (diff) | |
Added expand connect. Resolve now includes to working ir
Diffstat (limited to 'src/main/stanza')
| -rw-r--r-- | src/main/stanza/passes.stanza | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 6e8d89ad..a39c1287 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -29,6 +29,7 @@ public val standard-passes = to-list $ [ VerilogWrap() SplitExp() VerilogRename() + Resolve() ] ;=============== WORKING IR ================================ public definterface Kind @@ -1680,7 +1681,8 @@ defn resolve (c:Circuit) -> Circuit : resolve-genders $ check-types $ infer-types $ - resolve-kinds $ c + resolve-kinds $ + to-working-ir $ c ;;================= Inline Instances ======================== ;; Inlines instances. Assumes module with same name as the @@ -2892,10 +2894,3 @@ defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) : val c5 = verilog-rename(c4) ;println(c5) emit-verilog(with-output,c5) - - - - - - - |