From f1b5193353b6e021a0f5e5f33d5ac265f7bc686e Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 30 Jan 2016 13:45:43 -0800
Subject: Added expand connect. Resolve now includes to working ir

---
 src/main/stanza/passes.stanza | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

(limited to 'src/main/stanza')

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 6e8d89ad..a39c1287 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -29,6 +29,7 @@ public val standard-passes = to-list $ [
    VerilogWrap()
    SplitExp()
    VerilogRename()
+   Resolve()
 ]
 ;=============== WORKING IR ================================
 public definterface Kind
@@ -1680,7 +1681,8 @@ defn resolve (c:Circuit) -> Circuit :
    resolve-genders $
    check-types $
    infer-types $
-   resolve-kinds $ c
+   resolve-kinds $ 
+   to-working-ir $ c
 
 ;;================= Inline Instances ========================
 ;; Inlines instances. Assumes module with same name as the
@@ -2892,10 +2894,3 @@ defn lo-to-verilog (with-output:(() -> False) -> False, c:Circuit) :
    val c5 = verilog-rename(c4)
    ;println(c5)
    emit-verilog(with-output,c5)
-
-
-
-
-
-
-
-- 
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