diff options
| author | azidar | 2015-04-17 10:59:32 -0700 |
|---|---|---|
| committer | azidar | 2015-04-17 10:59:32 -0700 |
| commit | 01fa067fe52081463222110b957053734e357f79 (patch) | |
| tree | e54db5f543c4c9a84e6b120468c4008a4edac8d0 /src/main/stanza/firrtl-ir.stanza | |
| parent | 06ff7f7dddcb479d9d4d775a55cbb18d873b35b9 (diff) | |
Fixed bug in primop lowering during type inference. Added reduce instructions and renamed concat -> cat, equal -> eq, and added neq and neg
Diffstat (limited to 'src/main/stanza/firrtl-ir.stanza')
| -rw-r--r-- | src/main/stanza/firrtl-ir.stanza | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index d9105430..d4d12400 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -105,6 +105,9 @@ public val SHIFT-LEFT-S-OP = new PrimOp public val SHIFT-RIGHT-OP = new PrimOp public val SHIFT-RIGHT-U-OP = new PrimOp public val SHIFT-RIGHT-S-OP = new PrimOp +public val NEG-OP = new PrimOp +public val NEG-U-OP = new PrimOp +public val NEG-S-OP = new PrimOp public val CONVERT-OP = new PrimOp public val CONVERT-U-OP = new PrimOp public val CONVERT-S-OP = new PrimOp @@ -115,6 +118,9 @@ public val BIT-XOR-OP = new PrimOp public val CONCAT-OP = new PrimOp public val BIT-SELECT-OP = new PrimOp public val BITS-SELECT-OP = new PrimOp +public val BIT-AND-REDUCE-OP = new PrimOp +public val BIT-OR-REDUCE-OP = new PrimOp +public val BIT-XOR-REDUCE-OP = new PrimOp public definterface Expression public defmulti type (e:Expression) -> Type |