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path: root/src/main/scala/firrtl/passes
AgeCommit message (Expand)Author
2018-03-28Replace unconnected registers with 0 in Constant Propagation (#776)Jack Koenig
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-03-26Make WiringTransform remove its used annotations (#774)Schuyler Eldridge
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
2018-03-02Reduce Statement nesting in Wiring Pass (#751)Jack Koenig
2018-03-01[name change] Use LsbLargerThanMsbException (#740)Schuyler Eldridge
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-21Change primop arg type (#587)Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
2018-02-08CheckHighForm should check that Bits MSB >= LSB (#738)Schuyler Eldridge
2018-02-05Added comments to ExpandWhens (#716)Adam Izraelevitz
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
2017-12-27Removed top preamble (#640)Adam Izraelevitz
2017-12-22API change: out-of-bounds vec accesses now invalid, not first element (#685)Adam Izraelevitz
2017-12-20Verify shl/shr amount is > 0 (#710)Jim Lawson
2017-12-20Make submodule inputs void in ExpandWhens (#706)Jack Koenig
2017-09-30Make ReplaceAccesses optimize multi-dimensional accesses (#665)Albert Magyar
2017-09-30Fixed zero width cat but (#651)Adam Izraelevitz
2017-09-22Fix string lit (#663)Jack Koenig
2017-06-29Connect registers with no connections to zeroJack Koenig
2017-06-28Promote ConstProp to a transformJack Koenig
2017-06-26Add support for wires in ConstPropJack Koenig
2017-06-26Speed up ConstProp by doing ConstProp before recording nodeJack Koenig
2017-06-13Replace IsInvalids on LowForm with connection to zeroJack Koenig
2017-06-13Canonicalize spacing in RemoveValidIfJack Koenig
2017-06-13Make ExpandWhens delete 'is invalid' for attached Analog componentsJack Koenig
2017-06-12Move CheckCombLoops from passes/ to transforms/Jack Koenig
2017-06-12Change CheckCombLoops to a TransformJack Koenig
2017-05-27Prep for Scala 2.12 (#557)Jim Lawson
2017-05-25Fix performance bug in ZeroWidth (#594)Jack Koenig
2017-05-12Bugfix: renaming instance ports was broken. (#588)Adam Izraelevitz
2017-05-12Fix pad, second try (#465)Adam Izraelevitz
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-05-10Update rename2 (#478)Adam Izraelevitz
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
2017-04-13Speed up CSE by doing CSE on node expression before recording the node (#543)Jack Koenig
2017-04-04DecorateMems should not delete annoations (#523)Colin Schmidt
2017-04-03Find a single cycle from potentially many in a combinational SCCAlbert Magyar
2017-03-29Fix bug where zero width expressions in nodes wouldn't get zeroed (#514)Jack Koenig
2017-03-23Add pass to detect combinational loopsAlbert Magyar
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-22Fixed zero width perf bug #502Adam Izraelevitz
2017-03-22Fix unapply of pinAdam Izraelevitz
2017-03-22Bugfix: apply/unapply of PinAnnotation brokenazidar
2017-03-09make sure infer-rw works for exclusive when statements (#481)Donggyu
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
2017-03-06Zero width (#402)Adam Izraelevitz
2017-03-06Addresses #459. Rewords transform annotations API.Adam Izraelevitz
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