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Scala FIRRTL Compiler for chiselX
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2020-08-12
Combined Uniquify and LowerTypes pass (#1784)
Kevin Laeufer
2020-08-12
Strip dependencies from BlackBoxSourceHelper (#1840)
Schuyler Eldridge
2020-08-11
File Serialization of Annotations (#1277)
Schuyler Eldridge
2020-08-11
stage: allow a RunFirrtlTransformAnnotation(_:Emitter) annotation to be used ...
Kevin Laeufer
2020-08-07
ExpandWhens: VerificationStatements should be part of the simlist (#1829)
Kevin Laeufer
2020-08-06
Add deprecations for more firrtl.Compiler methods (#1791)
Schuyler Eldridge
2020-08-05
ir: add UseSerializer mixin trait (#1824)
Kevin Laeufer
2020-08-05
Deprecate InstanceGraph (#1800)
Kevin Laeufer
2020-08-01
Error on ExtModules w/ same defname, diff. ports (#1734)
Schuyler Eldridge
2020-07-31
Avoid repeated inlining in FlattenRegUpdate (#1727)
Jack Koenig
2020-07-31
CircuitGraph: remove fields from public API (#1813)
Kevin Laeufer
2020-07-31
[WIP] Implement CircuitGraph and IRLookup to firrtl.analyses (#1603)
Jiuyang Liu
2020-07-30
ir: use Serializer.serialize where possible (#1809)
Kevin Laeufer
2020-07-29
ManipulateNames: use composition instead of extending HashMap
Kevin Laeufer
2020-07-29
[2.13] fix legacy procedure syntax
Kevin Laeufer
2020-07-29
[2.13] use scala.collection.Seq instead of mutable.Seq
Kevin Laeufer
2020-07-29
PropagatePreset: use partition function to find other annotations
Kevin Laeufer
2020-07-29
[2.13] EmissionOptionMap now uses a HashMap instead of extending it
Kevin Laeufer
2020-07-29
[2.13] replace `= Unit` with `= ()`
Kevin Laeufer
2020-07-29
Compiler: clarify package of DedupModules
Kevin Laeufer
2020-07-29
MemConf: build list of tuples and turn it into a map at the end
Kevin Laeufer
2020-07-29
[2.13] convert toSeq and toMap where necessary to compile
Kevin Laeufer
2020-07-29
[2.13] explicitly use a parallel vector
Kevin Laeufer
2020-07-29
WiringTransform: fix non-determinism (#1799)
Kevin Laeufer
2020-07-29
RemoveWires: improve dependencies and declare ResolveKinds as an invalidation...
Kevin Laeufer
2020-07-29
InferTypes: fix bugs with unknown widths on ports and memories (#1769)
Kevin Laeufer
2020-07-28
Fix incorrect error message (#1795)
Andrew Waterman
2020-07-27
Add adapter to make current CHIRRTL mport scoping legal
Albert Magyar
2020-07-27
Honor block scoping of Conditionally in CheckHighForm
Albert Magyar
2020-07-25
Integrate new transforms with firrtl.stage.Forms (#1754)
Schuyler Eldridge
2020-07-24
Fix sign extension issue in Emitter (#1785)
Albert Chen
2020-07-23
fix reduction op bug ConstantPropagation (#1746)
Albert Chen
2020-07-23
mask bits when propagating bitwise ops (#1745)
Albert Chen
2020-07-23
Update negative literal emission (#1782)
Albert Chen
2020-07-20
Make InferWidths thread safe (#1775)
Schuyler Eldridge
2020-07-18
Faster dedup instance graph (#1732)
Kevin Laeufer
2020-07-17
Propagate source locators to register update always blocks (#1743)
Jack Koenig
2020-07-15
ir: store FileInfo string in escaped format (#1690)
Kevin Laeufer
2020-07-14
Make TopWiringTransform run before LowerTypes (#1750)
Schuyler Eldridge
2020-07-14
Delete outdated scalastyle configuration comments from source
Albert Magyar
2020-07-14
Fix parsing of info on multi-line registers (#1735)
Jack Koenig
2020-07-10
Remove Left Over References to Gender in Code (#1752)
Kevin Laeufer
2020-07-08
dedup: use structural sha256 hash instead of agnostify and serialize (#1731)
Kevin Laeufer
2020-07-08
ir: add faster serializer (#1694)
Kevin Laeufer
2020-07-07
verification: emit mesage as Verilog comment (#1712)
Kevin Laeufer
2020-07-01
Fix unchecked type in ManipulateNames (#1726)
Schuyler Eldridge
2020-06-26
Enable ConvertAsserts in default Verilog compiler
Albert Magyar
2020-06-26
Add ConvertAsserts transform to map asserts to Verilog-friendly nodes
Albert Magyar
2020-06-25
Batch renames in LowerTypes (#1718)
Schuyler Eldridge
2020-06-25
Add --change-name-case <lower|upper> option
Schuyler Eldridge
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