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AgeCommit message (Expand)Author
2020-06-25Add LetterCaseTransformsSchuyler Eldridge
2020-06-25Add ManipulateNamesAllowlistResultAnnotationSchuyler Eldridge
2020-06-25Refactor RemoveKeywordCollisions->ManipulateNamesSchuyler Eldridge
2020-06-24verification: clarify the meaning of verification statement in warning messag...Kevin Laeufer
2020-06-23Don't Dedup modules if it would change semantics (#1713)Jack Koenig
2020-06-23Basic model checking API (#1653)Tom Alcorn
2020-06-23Add support for ValidIf to ProtoBuf [de]serializationJack Koenig
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
2020-06-22Deprecate PreservesAllSchuyler Eldridge
2020-06-22Set prerequisite of -X high to MinimalHighForm (#1704)Schuyler Eldridge
2020-06-22Support Memory Initialization for Simulation and FPGA Flows (#1645)Kevin Laeufer
2020-06-22recore of Attributes (#1643)Jiuyang Liu
2020-06-19RemoveIntervals: invalidate InferTypes and ResolveKinds (#1689)Albert Chen
2020-06-12delete usages of toSet for determinism (#1686)Albert Chen
2020-06-11Compiler: demote compile time to info instead of error (#1685)Kevin Laeufer
2020-06-10Build ArrayBuffers in Block.mapStmt (#1669)Jack Koenig
2020-06-09Speed up ExpandWhens for very large designs (#1666)Jack Koenig
2020-06-04Make Utils.expandRef properly return intermediate expressionsAlbert Magyar
2020-06-03Use recursive-then-iterative approach for check_width_eAlbert Magyar
2020-06-03Revert: Generalize keyword collision to name manipulation, Add {Lower,Upper}C...Schuyler Eldridge
2020-06-03Add mapString method to ir.Port (#1655)Schuyler Eldridge
2020-06-03Scaladoc updates (#1656)Schuyler Eldridge
2020-06-02Update tutorial to reflect IR/WIR forms being mergedAlbert Magyar
2020-06-02Add extra convenience factories for regular IR nodesAlbert Magyar
2020-06-02Fix performance pathology in DedupModules (#1654)Jack Koenig
2020-05-28Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths (#1539)Albert Chen
2020-05-26Make WrappedTransform work with --class-log-level (#1640)Schuyler Eldridge
2020-05-26Cleanup unused imports (no-warning docs req from CI)Albert Magyar
2020-05-26Remove trivially dead code from now-redundant WIR/IR match patternsAlbert Magyar
2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
2020-05-22Do not throw NonFatal exceptions in annotation loggingJack Koenig
2020-05-22DRY out transform running and annotation remappingJack Koenig
2020-05-21RenameMap: remove implicit rename chaining (#1591)Albert Chen
2020-05-20Add scaladoc for LogicNode and tighten LowForm-only constraint (#1635)Albert Magyar
2020-05-18Don't try deduping the main module of a circuit (#1594)Albert Magyar
2020-05-18Fix equivalence tests (#853)Albert Chen
2020-05-18Canonicalize init of regs with zero as reset in RemoveReset (#1627)Albert Magyar
2020-05-14Make find_port return Unit and use Foreachers in ResolveKindsAlbert Magyar
2020-05-14Eliminate unnecessary traversals in ResolveKindsJack Koenig
2020-05-14Use HashMap instead of LinkedHashMap in ResolveKindsJack Koenig
2020-05-14Move Reg/Mem initializations to end of module (#1613)Deborah Soung
2020-05-13Remove accidental hashing of all Modules in DedupJack Koenig
2020-05-13Remove expensive .distinct in DedupJack Koenig
2020-05-13Remove a redundant Expression traversal in InferTypesJack Koenig
2020-05-13Use HashMap instead of LinkedHashMap in InferTypesJack Koenig
2020-05-13Add --change-name-case <lower|upper> optionSchuyler Eldridge
2020-05-13Add features.{LowerCaseNames, UpperCaseNames} transformsSchuyler Eldridge
2020-05-13Refactor RemoveKeywordCollisions->ManipulateNamesSchuyler Eldridge
2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
2020-05-11Have AppendInfo use MultiInfo, rather than appending with : (#1580)Adam Izraelevitz
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