Add features.{LowerCaseNames, UpperCaseNames} transforms

Creates the features package and populates it with two new transforms:
LowerCaseNames and UpperCaseNames. These transforms convert all names
in a FIRRTL circuit to lower case or upper case. This is intended to
help align generated Verilog with the policies of the
company/institution using it.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

squash! Add LowerCaseNames and UpperCaseNames transforms

2 files changed, 38 insertions, 2 deletions

diff --git a/src/main/scala/firrtl/features/LetterCaseTransform.scala b/src/main/scala/firrtl/features/LetterCaseTransform.scala
new file mode 100644
index 00000000..09bf6643
--- /dev/null
+++ b/src/main/scala/firrtl/features/LetterCaseTransform.scala
@@ -0,0 +1,38 @@
+// See LICENSE for license details.
+
+package firrtl.features
+
+import firrtl.{analyses, Namespace, passes, Transform}
+import firrtl.options.Dependency
+import firrtl.stage.Forms
+import firrtl.transforms.ManipulateNames
+
+/** Parent of transforms that do change the letter case of names in a FIRRTL circuit */
+abstract class LetterCaseTransform extends ManipulateNames {
+  override def prerequisites = Seq(Dependency(passes.LowerTypes))
+  override def optionalPrerequisites = Seq.empty
+  override def optionalPrerequisiteOf = Forms.LowEmitters
+  override def invalidates(a: Transform) = a match {
+    case _: analyses.GetNamespace => true
+    case _                        => false
+  }
+
+  protected def newName: String => String
+
+  final def condition = _ => true
+
+  final def manipulate = (a: String, ns: Namespace) => newName(a) match {
+    case `a` => a
+    case b   => ns.newName(b)
+  }
+}
+
+/** Convert all FIRRTL names to lowercase */
+final class LowerCaseNames extends LetterCaseTransform {
+  override protected def newName = (a: String) => a.toLowerCase
+}
+
+/** Convert all FIRRTL names to UPPERCASE */
+final class UpperCaseNames extends LetterCaseTransform {
+  override protected def newName = (a: String) => a.toUpperCase
+}
diff --git a/src/main/scala/firrtl/transforms/ManipulateNames.scala b/src/main/scala/firrtl/transforms/ManipulateNames.scala
index df6ad177..1d628881 100644
--- a/src/main/scala/firrtl/transforms/ManipulateNames.scala
+++ b/src/main/scala/firrtl/transforms/ManipulateNames.scala
@@ -6,9 +6,7 @@ import firrtl._
 import firrtl.analyses.InstanceGraph
 import firrtl.annotations.{Named, CircuitName, ModuleName, ComponentName}
 import firrtl.Mappers._
-import firrtl.options.Dependency
 import firrtl.passes.PassException
-import firrtl.stage.Forms
 
 import scala.collection.mutable