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AgeCommit message (Expand)Author
2021-04-05Merge pull request #2111 from chipsalliance/fpga-backendAlbert Magyar
2021-04-05Establish a fixed relative order for FPGA-backed passes + reflect in ScalaDocAlbert Magyar
2021-04-05Add test for SeparateWriteClocksAlbert Magyar
2021-04-05Add --target:fpga flag to prioritize FPGA-friendly compilationAlbert Magyar
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
2021-04-05Add tests for same-address readwrite inferenceAlbert Magyar
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
2021-04-05Allow direct emission of sync-read memories to VerilogAlbert Magyar
2021-04-05Specify that SimplifyMems invalidates InferTypesAlbert Magyar
2021-04-04Fix mill cache download (#2171)Jiuyang Liu
2021-04-01Add memory initialization options for synthesis (#2166)Carlos Eduardo
2021-03-30Fix Mill support for non-M1 Macs (#2165)Jack Koenig
2021-03-30Update README.md (#2164)Jack Koenig
2021-03-30don't use protoc-jar anymore, mill can handle it better. (#2162)Jiuyang Liu
2021-03-29Update protobuf-java to 3.15.6 (#2136)Scala Steward
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
2021-03-27Add NoConstantPropagationAnnotation to disable constatnt propagation (#2150)Jiuyang Liu
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
2021-03-25add scalafmt to mill (#2151)Jiuyang Liu
2021-03-22Fix mill compile and add to CI (#2147)Jiuyang Liu
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
2021-03-18Ensure InlineCasts does not inline complex Expressions (#2130)Jack Koenig
2021-03-16Fix issue where inlined cvt could cause crash (#2124)Jack Koenig
2021-03-14Fix width of constant propagation of SInt with zero (#2120)Jack Koenig
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
2021-03-11Fix CSESubAccesses for SubAccesses with flips (#2112)Jack Koenig
2021-03-09Fix the readmem statements in nested block (#2109)Carlos Eduardo
2021-03-09Create annotation to allow inline readmem in Verilog (#2107)Carlos Eduardo
2021-03-09SMT Backend: model Invalid and Division by Zero with DefRandom nodes (#2104)Kevin Laeufer
2021-03-08SMT: memory port inout fields cannot be used as RHS expressions (#2105)Kevin Laeufer
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
2021-03-04CSE SubAccesses (#2099)Jack Koenig
2021-03-03Fix ProtoBuf conversions for Verification IR (#2100)Deborah Soung
2021-03-02Remove Scala 2.11 (#2062)Jack Koenig
2021-03-02Fix CI Checks (#2097)Jack Koenig
2021-02-25Emit space after 'if' for all Verilog conditional synchronous assignments (#2...Albert Magyar
2021-02-17ExpandWhens: ensure that statement names are maintained (#2082)Kevin Laeufer
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
2021-02-16Merge pull request #2077 from chipsalliance/must-dedupJack Koenig
2021-02-16Add MustDeduplicateTransformJack Koenig
2021-02-16Add DiGraph factory method and prettyTreeJack Koenig
2021-02-05Add file line to source link from scaladoc (#2072)John's Brew
2021-02-03IR: turn some IR nodes into data classes (#2071)Kevin Laeufer
2021-02-01Suport ir.SubAccess in Utils.splitRef (#2021)Schuyler Eldridge
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
2021-02-01ConstantPropagation: make RemoveValidIf an optional dependency (#2027)Kevin Laeufer
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
2021-01-26Fix post-merge publishing (#2055)Jack Koenig
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