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path: root/src/main/scala/firrtl/passes
AgeCommit message (Expand)Author
2023-02-03Fix invalid references generated by VerilogMemDelays (#2588)Alan L
2022-12-150-bit literals (#2544)Kevin Laeufer
2022-04-07Make MemConf's MemPort serialization deterministic (#2508)Chick Markley
2022-03-02Fold VerilogModulusCleanup into LegalizeVerilog (#2485)Jack Koenig
2021-12-21Remove some warnings (#2448)Jack Koenig
2021-12-18Fix width of signed addition when input to mux (#2440)Jack Koenig
2021-12-17Deprecate all mutable methods on RenameMap (#2444)Jack Koenig
2021-10-04Hotfix for Vector Reg Init LegalizeConnects BugSchuyler Eldridge
2021-09-29Have Flatten & InlineInstances remove their annotations (#2374)David Biancolin
2021-09-11Remove BlackBoxSourceHelper from ReplaceMemTransform (#2355)Jack Koenig
2021-09-10MemConf: Do not add another new line when serializing (#2354)Megan Wachs
2021-08-26Fix dshl zero-width shift behavior (#2339)Schuyler Eldridge
2021-08-13Modify NoCommonSubexpressionElimination to NoCommonSubexpressionEliminationAn...胡波
2021-08-09Implement NoCommonSubexpressionElimination (#2291)Jiuyang Liu
2021-08-03Require Andr, Orr, Xorr, Neg to have one operand (#2312)Schuyler Eldridge
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
2021-06-22Fix VerilogMemDelays use before declaration (#2278)Jack Koenig
2021-06-03Replace mem macros renaming (#2243)Albert Chen
2021-05-22Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)sinofp
2021-05-21Fix renaming of local targets in InlineInstances (#2238)Albert Chen
2021-05-21WiringTransform: cannot run after RemoveWires (#2240)Kevin Laeufer
2021-05-18Improve performance of RenameMap in LowerTypes (#2233)Jack Koenig
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-22Fix CheckWidths error message for uninferred width (#2196)Fabian Schuiki
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-04-06Deprecate InlineCasts, add InlineAcrossCasts (#2146)Jack Koenig
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
2021-03-04CSE SubAccesses (#2099)Jack Koenig
2021-02-17ExpandWhens: ensure that statement names are maintained (#2082)Kevin Laeufer
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
2021-01-26Fix post-merge publishing (#2055)Jack Koenig
2021-01-20Cleanup some warnings (#2032)Jack Koenig
2020-12-15Improve performance of LowerTypes renaming (#2024)Jack Koenig
2020-12-02Fix subaccess (#1984)Jiuyang Liu
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
2020-11-10Refactor emiter (#1879)Jiuyang Liu
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-28FlattenSpec: flattening a module with no instaces should be a no-op (#1868)Kevin Laeufer
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