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2023-02-03Fix invalid references generated by VerilogMemDelays (#2588)Alan L
Transformation of mem readwriters whose address contain references to readwriters of mems declared before it would contain invalid references to untransformed memory readwriter, as the connection is not transformed. This commit fixes this issue.
2022-12-150-bit literals (#2544)Kevin Laeufer
* allow for zero-width integer literals * CheckWidths: ensure that width is non-negative
2022-04-07Make MemConf's MemPort serialization deterministic (#2508)Chick Markley
Problem: MemConf serialization of MemPorts was not deterministic and the ordering seems to have changed as we move projects to 2.13 Downstream project can be adversely affected by changes in ordering This changes specifies as specific ordering that should be compatible with the historical one.
2022-03-02Fold VerilogModulusCleanup into LegalizeVerilog (#2485)Jack Koenig
This fixes handling of signed modulus and removes some redundant work.
2021-12-21Remove some warnings (#2448)Jack Koenig
* Fix unreachable code warning by changing match order Simulation Statements did not previously extend IsDeclaration, but now they do so their match blocks need to be above IsDeclaration. * Handle MemoryNoInit case in RtlilEmitter * Remove use of deprecated logToFile * Fix uses of LegalizeClocksTransform Replaced all uses of LegalizeClocksTransform with LegalizeClocksAndAsyncResetsTransform. * Remove use of CircuitForm in ZeroWidth
2021-12-18Fix width of signed addition when input to mux (#2440)Jack Koenig
Fix bugs related to arithmetic ops inlined into a mux leg. Add formal equivalence checks to lock in this behavior. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-12-17Deprecate all mutable methods on RenameMap (#2444)Jack Koenig
* Add renamemap.MutableRenameMap which includes these methods without deprecation * Deprecate Stringly typed RenameMap APIs which were accidentally undeprecated a while ago Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-10-04Hotfix for Vector Reg Init LegalizeConnects BugSchuyler Eldridge
Add a private pass, LegalizeConnectsOnly, that behaves like LegalizeConnects, but only pads connects instead of connects and register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem runs before LowerTypes and vector registers can still exist at this point. Connects, conversely, are all blown out by ExpandConnects and can be safely, blindly treated as ground type. Fixes #2379. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-09-29Have Flatten & InlineInstances remove their annotations (#2374)David Biancolin
* Have Flatten & InlineInstances remove their annotations * Format
2021-09-11Remove BlackBoxSourceHelper from ReplaceMemTransform (#2355)Jack Koenig
BlackBoxSourceHelper should only run late in compilation to allow transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
2021-09-10MemConf: Do not add another new line when serializing (#2354)Megan Wachs
2021-08-26Fix dshl zero-width shift behavior (#2339)Schuyler Eldridge
* Fix dshl zero-width shift behavior Add a special case for dshl handling in the ZeroWidths pass. If one expression is shifted by a second, zero-width expression, just return the first expression. This prevents a bug where the width will incorrectly expand due to zero-widths introducing a 1-bit zero expression. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Fix dshl zero-width shift behavior
2021-08-13Modify NoCommonSubexpressionElimination to ↵胡波
NoCommonSubexpressionEliminationAnnotation (#2329) to make it has the same form with NoDCEAnnotation and NoConstantPropagationAnnotation
2021-08-09Implement NoCommonSubexpressionElimination (#2291)Jiuyang Liu
* implement NoCommonSubexpressionElimination to resolve chipsalliance/chisel3#2006 * Update src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-03Require Andr, Orr, Xorr, Neg to have one operand (#2312)Schuyler Eldridge
Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number of operands. Verilog emission doesn't support this and will silently drop all operands after the first. E.g., "andr(a, b)" would emit as "&a". After this commit, "andr(a, b)" will be rejected by checking passes. For archaeological purposes, this appears to have been the behavior dating back to when this was added in d2d3260a. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
* rearrange passes to enable optimized firrtl emission * Support ConstProp on padded arguments to comparisons with literals * Move shr legalization logic into ConstProp Continue calling ConstProp of shr in Legalize. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-06-22Fix VerilogMemDelays use before declaration (#2278)Jack Koenig
The pass injects pipe registers immediately after the declaration of the memory. This can be problematic if the clock for the associated memory port is defined after the declaration of the memory. For any memory port clocks that are driven by non-ports, we now inject a wire before the pipe register declarations to be sure there are no use-before-declaration issues.
2021-06-03Replace mem macros renaming (#2243)Albert Chen
* ReplaceMemMacros: add target rename test case * ReplaceMemMacros: rename references to instances * fix renaming for deduped mems * use grouped DummyAnnos to preserve order * Apply suggestions from code review Co-authored-by: Jack Koenig <koenig@sifive.com> * run scalafmt * flatten targets Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-05-22Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)sinofp
* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen * Add CLI support for GenVerilogMemBehaviorModelAnno * Add simple test for GenVerilogMemBehaviorModelAnno * Fix for review 1. rename case class Port(prefix, `type`) to Port(prefix, portType) 2. fix AnnotatedMemoriesAnnotation collect function. 3. fix bug that ModuleName is not correct. * Format DumpMemoryAnnotations & ReplSeqMemTests * Fix for review 1. Inline genDecl, genPortSpec, genSequential, genCombinational 2. Add DefAnnotatedMemory informations in header 3. Change helpText 4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog * Fix ReadWritePort mask name Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-21Fix renaming of local targets in InlineInstances (#2238)Albert Chen
* add more inline renaming test cases * InlineInstances: fix renaming for local targets * run scalafmt Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-05-21WiringTransform: cannot run after RemoveWires (#2240)Kevin Laeufer
2021-05-18Improve performance of RenameMap in LowerTypes (#2233)Jack Koenig
LowerTypes creates a lot of mappings for the RenameMap. The built-in .distinct of renames becomes a performance program for designs with deeply nested Aggregates. Because LowerTypes does not create duplicate renames, it can safely eschew the safety of using .distinct via a private internal API.
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
* remove all deprecations, switch to new API. * Add MemLibOutConfigFileAnnotation to replace ConfWriter. * Inline CreateMemoryAnnotations in ReplSeqMem. * Dont use ConfWriter anymore. * Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation. * Fix for review. 0. Since DependencyAPI only initiate transform only once, ListBuffer is dangerous to use, remove defAnnotatedMemories from Transform. 1. Add trait HasAnnotatedMemories to store ListBuffer, MemLibOutConfigFileAnnotation also extends from which now. * Use two annotations converting and storing DefMemory. 0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation creating PinAnnotation. 1. add DumpMemoryAnnotations to convert from AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation 2. refactor MemLibOutConfigFileAnnotation and remove HasAnnotatedMemories 3. add private AnnotatedMemoriesCollectorAnnotation to store mutable DefAnnotatedMemory 4. change ReplSeqMem to SeqTransform * Fix for review. 0. replace AnnotatedMemoriesCollectorAnnotation with immutable AnnotatedMemoriesAnnotation. 1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute. * private functions in ReplaceMemMacros transform. * scalafmt * remove ConfWriter API.
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-22Fix CheckWidths error message for uninferred width (#2196)Fabian Schuiki
Looks like a typo/auto-merge hiccup.
2021-04-16Make InferTypes error on enable conditions > 1-bit wide (#2182)Jack Koenig
2021-04-06Deprecate InlineCasts, add InlineAcrossCasts (#2146)Jack Koenig
To maintain binary compatibility, InlineAcrossCasts is just aliases to the now deprecated InlineCasts. We can make the binary incompatible change of renaming the class and object for 1.5. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
* Address @ekiwi comments from review * Change match cases to scalafmt-mandated lined-up style
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
* Optionally defines read-under-write behavior for all 'undefined' memories * Use DefaultReadFirstAnnotation to choose read-first default * Use DefaultWriteFirstAnnotation to choose write-first default * Seal DefaultReadUnderWriteAnnotation based on Jack's feedback
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
* This is enabled by adding a PassthroughSimpleSyncReadMemsAnnotation * Can be emitted directly with new changes to the Verilog emitter * Add some new deprecations to VerilogMemDelays * Run scalafmt on VerilogMemDelays
2021-03-29Fix RemoveAccesses, delete CSESubAccesses (#2157)Jack Koenig
CSESubAccesses was intended to be a simple workaround for a quadratic performance bug in RemoveAccesses but ended up having tricky corner cases and was hard to get right. The solution to the RemoveAccesses bug--quadratic expansion of dynamic indexes of vecs of aggreate type--turned out to be quite simple and makes CSESubAccesses much less useful and not worth fixing. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-03-26Fix bug in zero-width memory removal (#2153)Schuyler Eldridge
* Fix bug in zero-width memory removal Correctly remove all extraneous connections to all types of memory ports (read, write, readwrite) for zero-width memories. Previously, only read ports were correctly handled. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Fix bug in zero-width memory removal
2021-03-19Legalize neg: -x becomes 0 - x (#2128)Jack Koenig
This fixes an error with negating a negative SInt literal and a [debatable] lint warning in Verilator when negating any value. This behavior matches that of Chisel (which directly emits the 0 - x already).
2021-03-14Fix cat of zero-width SInt (#2116)Jack Koenig
Previously, concatenating two SInts where one is of zero-width would return the non-zero-width SInt. This is incorrect because the output of Cat should be of type UInt. Now the ZeroWidth transform will introduce a cast when removing a Cat when the argument type is non-UInt.
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
With this PR the smt backend now supports memories with more than two write ports and the conservative memory modelling can be selectively turned off with a new annotation.
2021-03-04CSE SubAccesses (#2099)Jack Koenig
Fixes n^2 performance problem when dynamically indexing Vecs of aggregate types. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-02-17ExpandWhens: ensure that statement names are maintained (#2082)Kevin Laeufer
2021-02-17Allow Side Effecting Statement to have Names (#2057)Kevin Laeufer
* firrtl: add optional statement labels for stop, printf, assert, assume and cover * test: parsing of statement labels * ir: ensure that name is properly retained * SymbolTable: add support for labled statements * test: parsing statement labels * test: lower types name collisions with named statements * ignore empty names * Inline: deal with named and unnamed statements * RemoveWires: treat stop, printf and verification statements as "others" * test: fix InlineInstance tests * DeadCodeEliminations: statements are now als declarations * CheckHighForm: ensure that statement names are not used as references * CheckSpec: throw error if statement name collides * add pass to automatically add missing statement names * check: make sure that two statements cannot have the same name * stmtLabel -> stmtName * scalafmt * add statement names to spec * spec: meta data -> metadata * EnsureStatementNames: explain naming algorithm * remove returns * better namespace use * ir: add CanBeReferenced trait * ir: add newline as jack requested
2021-02-01Deprecate ToWorkingIR (#2028)Schuyler Eldridge
* Deprecate firrtl.passes.ToWorkingIR Deprecate ToWorkingIR as it is now an identity transform. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Deprecate firrtl.stage.Forms.WorkingIR Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> * Switch from Forms.WorkingIR to Forms.MinimalHighForm Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-01-28Stop padding multiply and divide ops (#2058)Jack Koenig
Fixes bug with mul or div followed by cat. Also fixes some Verilog lint issues.
2021-01-26Fix post-merge publishing (#2055)Jack Koenig
* Check Unidoc on all versions of Scala It is required for publishing and we publish every version * Fix conflicting cross-version suffixes issue When running `sbt ++2.13.4 unidoc`, SBT would set the Scala version for the fuzzer and benchmark projects even though they aren't really relevant to the command. This may be a misconfiguration or a bug in the unidoc plugin. Whatever the case, simply making it possible for them to use the same version of Scala as the firrtl project (on which they depend) fixes the issue. * Match versions of Scala in build.sbt and CI * Fix unidoc issues in 2.13.4 There is some bug in ScalaDoc not finding some links in firrtl.options so those links were made absolute as a workaround.
2021-01-20Cleanup some warnings (#2032)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-12-15Improve performance of LowerTypes renaming (#2024)Jack Koenig
This is done by having LowerTypes uses two RenameMaps instead of one for each module. There is one for renaming instance paths, and one for renaming everything within modules. Also add some utilities: * TargetUtils for dealing with InstanceTargets * RenameMap.fromInstanceRenames
2020-12-02Fix subaccess (#1984)Jiuyang Liu
* add test for RemoveAccessesSpec. * fix nested SubAccess bug. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-11-12Fix RemoveWires handling of invalidated non-UInt wires (#1949)Jack Koenig
It would replace them with a validif node with a UIntLiteral which can lead to type errors.
2020-11-10Refactor emiter (#1879)Jiuyang Liu
* split big Emitter to submodules. * fix all deprecated warning. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-28FlattenSpec: flattening a module with no instaces should be a no-op (#1868)Kevin Laeufer
* FlattenSpec: flattening a module with no instaces should be a no-op * Fix problem when flattening/inlining a lone module Fix an edge case bug in InlineInstances where a circuit containing a lone module is flattened/inlined. This now properly special cases the situation of an empty indexMap which before had to be of length >= 1. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Simplify rename logic in InlineInstances Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Mea culpa Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
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