sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2020-09-16	Change to Apache 2.0 License (#1901)	Chick Markley

2020-08-14	All of src/ formatted with scalafmt	chick

2019-10-18	Upstream intervals (#870)	Adam Izraelevitz
	Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-09-30	Implement read-first memories in VerilogMemDelays	Albert Magyar
	* Corrects behavior under write collisions * Avoids heavily refactoring pass
2019-09-16	Rename gender to flow	Schuyler Eldridge
	The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-06-18	Use scalafix to remove unused import and deprecated procedure syntax (#1074)	Leway Colin
	* Add sbt-scalafix * Add scalafix guide to README * Remove Unused Import * Remove deprecated procedure syntax
2018-11-26	Make return types of util functions more specific (#949)	Albert Magyar

2018-03-19	Masks for zero-width fields of mems should be width zero. (#763)	grebe
	Closes #666.
2017-02-23	move more general utils out of memutils, mov WIR helpers to WIR.scala and ↵	Angie
	update uses
2017-02-23	messed up clocktype match	Angie

2017-02-23	added more helpers	Angie

2017-01-27	Fix signed types (#422)	Angie Wang
	* type conversions between sint/fixed and uint added at memory interfaces for replseqmem * turns out asFixed requires bp as constant in PrimOps (really should be documented) * fixed legalizeconnects to handle FixedPt * added tests for replseqmem failure with signed types
2016-10-24	match fromBits order with toBits, toBitMask (#349)	Donggyu

2016-10-23	Fix bitmask (#346)	Angie Wang
	* toBitMask cat direction should be consistent with data * minor comment updates * moved remaining mem passes/utils to memlib * changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated