aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes/memlib
AgeCommit message (Collapse)Author
2023-02-03Fix invalid references generated by VerilogMemDelays (#2588)Alan L
Transformation of mem readwriters whose address contain references to readwriters of mems declared before it would contain invalid references to untransformed memory readwriter, as the connection is not transformed. This commit fixes this issue.
2022-04-07Make MemConf's MemPort serialization deterministic (#2508)Chick Markley
Problem: MemConf serialization of MemPorts was not deterministic and the ordering seems to have changed as we move projects to 2.13 Downstream project can be adversely affected by changes in ordering This changes specifies as specific ordering that should be compatible with the historical one.
2021-12-17Deprecate all mutable methods on RenameMap (#2444)Jack Koenig
* Add renamemap.MutableRenameMap which includes these methods without deprecation * Deprecate Stringly typed RenameMap APIs which were accidentally undeprecated a while ago Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-10-04Hotfix for Vector Reg Init LegalizeConnects BugSchuyler Eldridge
Add a private pass, LegalizeConnectsOnly, that behaves like LegalizeConnects, but only pads connects instead of connects and register inits. Padding is necessary for ReplSeqMem, but ReplSeqMem runs before LowerTypes and vector registers can still exist at this point. Connects, conversely, are all blown out by ExpandConnects and can be safely, blindly treated as ground type. Fixes #2379. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
2021-09-11Remove BlackBoxSourceHelper from ReplaceMemTransform (#2355)Jack Koenig
BlackBoxSourceHelper should only run late in compilation to allow transforms to tweak its behavior (eg. changing BlackBoxTargetDirAnno).
2021-09-10MemConf: Do not add another new line when serializing (#2354)Megan Wachs
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
* rearrange passes to enable optimized firrtl emission * Support ConstProp on padded arguments to comparisons with literals * Move shr legalization logic into ConstProp Continue calling ConstProp of shr in Legalize. Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-06-22Fix VerilogMemDelays use before declaration (#2278)Jack Koenig
The pass injects pipe registers immediately after the declaration of the memory. This can be problematic if the clock for the associated memory port is defined after the declaration of the memory. For any memory port clocks that are driven by non-ports, we now inject a wire before the pipe register declarations to be sure there are no use-before-declaration issues.
2021-06-03Replace mem macros renaming (#2243)Albert Chen
* ReplaceMemMacros: add target rename test case * ReplaceMemMacros: rename references to instances * fix renaming for deduped mems * use grouped DummyAnnos to preserve order * Apply suggestions from code review Co-authored-by: Jack Koenig <koenig@sifive.com> * run scalafmt * flatten targets Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-05-22Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)sinofp
* Add GenVerilogMemBehaviorModelAnno & vlsiMemGen * Add CLI support for GenVerilogMemBehaviorModelAnno * Add simple test for GenVerilogMemBehaviorModelAnno * Fix for review 1. rename case class Port(prefix, `type`) to Port(prefix, portType) 2. fix AnnotatedMemoriesAnnotation collect function. 3. fix bug that ModuleName is not correct. * Format DumpMemoryAnnotations & ReplSeqMemTests * Fix for review 1. Inline genDecl, genPortSpec, genSequential, genCombinational 2. Add DefAnnotatedMemory informations in header 3. Change helpText 4. Check output Verilog by Verilator, the code is from FirrtlRunners#lintVerilog * Fix ReadWritePort mask name Co-authored-by: Jiuyang Liu <liu@jiuyang.me> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
* remove all deprecations, switch to new API. * Add MemLibOutConfigFileAnnotation to replace ConfWriter. * Inline CreateMemoryAnnotations in ReplSeqMem. * Dont use ConfWriter anymore. * Fix ReplSeqMemTests, rewrite checkMemConf to directly read from annoation. * Fix for review. 0. Since DependencyAPI only initiate transform only once, ListBuffer is dangerous to use, remove defAnnotatedMemories from Transform. 1. Add trait HasAnnotatedMemories to store ListBuffer, MemLibOutConfigFileAnnotation also extends from which now. * Use two annotations converting and storing DefMemory. 0. rewrite CreateMemoryAnnotations to match ReplSeqMemAnnotation creating PinAnnotation. 1. add DumpMemoryAnnotations to convert from AnnotatedMemoriesCollectorAnnotation to MemLibOutConfigFileAnnotation 2. refactor MemLibOutConfigFileAnnotation and remove HasAnnotatedMemories 3. add private AnnotatedMemoriesCollectorAnnotation to store mutable DefAnnotatedMemory 4. change ReplSeqMem to SeqTransform * Fix for review. 0. replace AnnotatedMemoriesCollectorAnnotation with immutable AnnotatedMemoriesAnnotation. 1. add ListBuffer[DefAnnotatedMemory] in ReplaceMemMacros.execute. * private functions in ReplaceMemMacros transform. * scalafmt * remove ConfWriter API.
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
* Address @ekiwi comments from review * Change match cases to scalafmt-mandated lined-up style
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
* Optionally defines read-under-write behavior for all 'undefined' memories * Use DefaultReadFirstAnnotation to choose read-first default * Use DefaultWriteFirstAnnotation to choose write-first default * Seal DefaultReadUnderWriteAnnotation based on Jack's feedback
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
* This is enabled by adding a PassthroughSimpleSyncReadMemsAnnotation * Can be emitted directly with new changes to the Verilog emitter * Add some new deprecations to VerilogMemDelays * Run scalafmt on VerilogMemDelays
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
With this PR the smt backend now supports memories with more than two write ports and the conservative memory modelling can be selectively turned off with a new annotation.
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-21Fix Uniquify bug and improve ReplaceSeqMems transforms (#1855)Jack Koenig
* Fix bug in Uniquify clobbering DefInstance types * Change ReplaceMemTransform to not run Uniquify nor fixups Use invalidation as mechanism for rerunning resolution passes
2020-08-14All of src/ formatted with scalafmtchick
2020-08-13Remove LegacyAnnotation and [most] MoultingYaml (#1833)Jack Koenig
* Remove LegacyAnnotation and MoultingYaml It has been deprecated since 1.1 * Remove all uses of ConvertLegacyAnnotations Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
* ir: use Serializer.serialize where possible * ir.Serializer: serialize MultiInfo correctly * ir.Serializer: empty body needs to result in a skip statement The firrtl grammar requires at least one statement. * ir.Serializer: correctly serialize fixed point types and literals * Serializer: change Seq -> Iterable in order to be Scala 2.13 compatible
2020-07-29[2.13] replace `= Unit` with `= ()`Kevin Laeufer
2020-07-29MemConf: build list of tuples and turn it into a map at the endKevin Laeufer
2020-07-29[2.13] convert toSeq and toMap where necessary to compileKevin Laeufer
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
This adds missing invalidations to four transforms: - ExpandConnects - RemoveAccesses - SplitExpressions - VerilogMemDelays This necessarily updates test cases which expect exact transform orders to reflect the new order. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
This reverts commit eabc38559b7634ff7147aa0ab3d71e78558d5162.
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
* Consume NoDedupMemAnnotations in ResolveMemoryReference The ComponentName being pointed to by the annotation no longer exists after ReplaceSeqMems so we should consume the annotations * Support renaming in ReplaceMemMacros Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-12Support MemConfs with very deep memories (#1367)Jerry Zhao
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
* Types containing bundles can't generally be converted to a single mask granularity * Update ReplSeqMemTests to check for illegal masks
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
* Closes #1242
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
* Additional refactoring to clean up pass implementation * Make register names match old scheme to appease CI
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
* Corrects behavior under write collisions * Avoids heavily refactoring pass
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
* Stop ignoring read-under-write (RUW) parameter * Add conservative check: blackbox only when RUW is "undefined" * VerilogMemDelays now throws InternalError for read-first memories * Previously, read-first mems were incorrectly implemented as write-first
2019-09-30Improve read-under-write parameter supportAlbert Magyar
* Make the read-under-write (RUW) parameter typesafe * Add RUW support to the FIRRTL proto and CHIRRTL grammar
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-01Followup to PR #1142chick
Fixes a threading bug in where lazy reading of file caused a problem for multithreaded access to the that was read. Changes all uses of io.Source to use new API getText getLines getTextResource getLinesResouce Make style to only import FileUtils and not its methods So code is more explicit as e.g. FileUtils.getText()
2019-07-08Remove some warnings (#1118)Leway Colin
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
* Add sbt-scalafix * Add scalafix guide to README * Remove Unused Import * Remove deprecated procedure syntax
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
Abstracts away option writing such that users no longer have to understand scopt semantics. This adds a ShellOption class and a HasShellOptions trait for something which provides one or more ShellOptions. This refactors the FIRRTL codebase to use this style of option specification. Adds and uses DeletedWrapper to automatically generate DeletedAnnotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-04-25Add FirrtlStage, make Driver compatibility layerSchuyler Eldridge
This adds FirrtlStage, a reimplementation of the original FIRRTL Driver as a Stage. This updates the original firrtl.options package to implement FirrtlStage (namely, TransformLike is added) along with FirrtlMain. Finally, the original FIRRTL Driver is converted to a compatibility wrapper around FirrtlStage. For background, Stage and Phase form the basis of the Chisel/FIRRTL Hardware Compiler Framework (HCF). A Phase is a class that performs a mathematical transformation on an AnnotationSeq (in effect, a generalization of a FIRRTL transform). Curtly, a Stage is a Phase that also provides a user interface for generating annotations. By their construction, Phases are designed to be composed sequentially into a transformation pipeline. This modifies the existing options package (which provides Stage/Phase) to build out a type hierarchy around Stage/Phase. This adds TransformLike[A] which implements a mathematical transformation over some type A. Additionally, and as an interface between different TransformLikes, this adds Translator[A, B] which extends TransformLike[A], but does an internal transformation over type B. This is used to interface Phases with the existing FIRRTL compiler. This adds a runTransform method to Phase that, like Transform.runTransform, will automatically detect deleted Annotations and generate DeletedAnnotations. The new FirrtlStage, a reimplementation of FIRRTL's Driver, is added as a Stage composed of the following Phases: 1. AddDefaults - add default annotations 2. AddImplicitEmitter - adds an implicit emitter derived from the compiler 3. Checks - sanity check the AnnotationSeq 4. AddCircuit - convert FIRRTL input files/sources to circuits 5. AddImplicitOutputFile - add a default output file 6. Compiler - run the FIRRTL compiler 7. WriteEmitted - write any emitted modules/circuits to files The Driver is converted to a compatibility layer that replicates old Driver behavior. This is implemented by first using new toAnnotation methods for CommonOptions and FirrtlExecutionOptions that enable AnnotationSeq generation. Second, the generated AnnotationSeq is preprocessed and sent to FirrtlStage. The resulting Phase order is then: 1. AddImplicitAnnotationFile - adds a default annotation file 2. AddImplicitFirrtlFile - adds a default FIRRTL file using top name 3. AddImplicitOutputFile - adds an output file from top name 4. AddImplicitEmitter - adds a default emitter derived from a compiler and any split modules command line option 5. FirrtlStage - the aforementioned new FirrtlStage Finally, the output AnnotationSeq is then viewed as a FirrtlExecutionResult. This compatibility layer enables uninterrupted usage of old Driver infrastructure, e.g., FirrtlExecutionOptions and CommonOptions can still be mutated directly and used to run the Driver. This results in differing behavior between the new FirrtlStage and the old Driver, specifically: - FirrtlStage makes a clear delineation between a "compiler" and an "emitter". These are defined using separate options. A compiler is "-X/--compiler", while an emitter is one of "-E/--emit-circuit" or "-e/--emit-modules". - Related to the above, the "-fsm/--split-modules" has been removed from the FirrtlStage. This option is confusing once an implicit emitter is removed. It is also unclear how this should be handled once the user can specify multiple emitters, e.g., which emitter should "--split-modules" apply to? - WriteOutputAnnotations will, by default, not write DeletedAnnotations to the output file. - The old top name ("-tn/--top-name") option has been removed from FirrtlStage. This option is really a means to communicate what input and output files are as opposed to anything associated with the circuit name. This option is preserved for the Driver compatibility layer. Additionally, this changes existing transform scheduling to work for emitters (which subclass Transform). Previously, one emitter was explicitly scheduled at the end of all transforms for a given compiler. Additional emitters could be added, but they would be scheduled as transforms. This fixes this to rely on transform scheduling for all emitters. In slightly more detail: 1. The explicit emitter is removed from Compiler.compile 2. An explicit emitter is added to Compiler.compileAndEmit 3. Compiler.mergeTransforms will schedule emitters as late as possible, i.e., all emitters will occur after transforms that output their input form. 4. All AddImplicitEmitter phases (DriverCompatibility and normal) will add RunFirrtlTransformAnnotations to add implicit emitters The FIRRTL fat jar utilities are changed to point at FirrtlStage and not at the Driver. This has backwards incompatibility issues for users that are using the utilities directly, e.g., Rocket Chip. The Logger has been updated with methods for setting options based on an AnnotationSeq. This migrates the Logger to use AnnotationSeq as input parameters, e.g., for makeScope. Old-style methods are left in place and deprecated. However, the Logger is not itself a Stage. The options of Logger Annotations are included in the base Shell and Stage is updated to wrap its Phases in a Logger scope. Additionally, this changes any code that does option parsing to always prepend an annotation as opposed to appending an annotation. This is faster, but standardizing on this has implications for dealing with the parallel compilation annotation ordering. A Shell will now put the initial annotations first (in the order the user specified) and then place all annotations generating from parsing after that. This adds a test case to verify this behavior. Discovered custom transforms (via `RunFirrtlTransformAnnotation`s) are discovered by the compiler phase in a user-specified order, but are stored in reverse order to more efficiently prepend (as opposed to append) to a list. This now reverses the transform order before execution to preserve backwards compatibility of custom transform ordering. The Compiler phase also generates one deleted annotation for each `RunFirrtlTransformAnnotation`. These are also reversed. Miscellaneous small changes: - Split main method of Stage into StageMain class - Only mix in HasScoptOptions into Annotation companion objects (h/t @jackkoenig) - Store Compiler in CompilerAnnotation - CompilerNameAnnotation -> CompilerAnnotation - Make Emitter abstract in outputSuffix (move out of FirrtlOptions) - Add DriverCompatibility.AddImplicitOutputFile that will add an output file annotation based on the presence of a TopNameAnnotation. This is important for compatibility with the old Driver. - Cleanup Scaladoc - Refactor CircuitOption to be abstract in "toCircuit" that converts the option to a FirrtlCircuitAnnotation. This allows more of the conversion steps to be moved out of AddCircuit and into the actual annotation. - Add WriteDeletedAnnotation to module WriteOutputAnnotations - A method for accessing a FirrtlExecutionResultView is exposed in FIRRTL's DriverCompatibilityLayer - Using "--top-name/-tn" or "--split-modules/-fsm" with FirrtlStage generates an error indicating that this option is no longer supported - Using FirrtlStage without at least one emitter will generate a warning - Use vals for emitter in Compiler subclasses (these are used to build RunFirrtlTransformAnnotations and the object should be stable for comparisons) - Fixes to tests that use LowTransformSpec instead of MiddleTransformSpec. (SimpleTransformSpec is dumb and won't schedule transforms correctly. If you rely on an emitter, you need to use the right transform spec to test your transform if you're relying on an emitter.) Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-03-19Designs with no SeqMems should produce empty MemConf strings, and this ↵John Wright
should be parsable without excepting (#1060)
2019-03-07Add a data structure for memory conf reading and writing (#1041)John Wright
* Copy MemConf.scala from ucb-bar/barstools#35 into memlib. This provides a data structure wrapper around the existing memory conf format which contains both reading and writing methods, making it easier to write code that needs to read the format. * Add MemConf tests and use a Map[MemPort, Int] for port lists instead of a Seq[MemPort] which is a bit less fragile.
generated by cgit v1.2.3 (git 2.25.1) at 2026-01-31 21:23:12 +0000