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path: root/src/main/scala/firrtl/passes/memlib
AgeCommit message (Expand)Author
2023-02-03Fix invalid references generated by VerilogMemDelays (#2588)Alan L
2022-04-07Make MemConf's MemPort serialization deterministic (#2508)Chick Markley
2021-12-17Deprecate all mutable methods on RenameMap (#2444)Jack Koenig
2021-10-04Hotfix for Vector Reg Init LegalizeConnects BugSchuyler Eldridge
2021-09-11Remove BlackBoxSourceHelper from ReplaceMemTransform (#2355)Jack Koenig
2021-09-10MemConf: Do not add another new line when serializing (#2354)Megan Wachs
2021-08-02add emitter for optimized low firrtl (#2304)Kevin Laeufer
2021-06-22Fix VerilogMemDelays use before declaration (#2278)Jack Koenig
2021-06-03Replace mem macros renaming (#2243)Albert Chen
2021-05-22Rewrite vlsi_mem_gen into a Firrtl Transform (#2202)sinofp
2021-04-27Memlib Refactor (#2191)Jiuyang Liu
2021-04-27deprecate memlib APIs modifided in #2191. (#2199)Jiuyang Liu
2021-04-05Add SeparateWriteClocks to ensure one mem write per Verilog processAlbert Magyar
2021-04-05Allow InferReadWrite to combine shared-address R/W ports when appropriateAlbert Magyar
2021-04-05Add SetDefaultReadUnderWrite transformAlbert Magyar
2021-04-05Optionally allow simple SyncReadMems to pass through VerilogMemDelaysAlbert Magyar
2021-03-04SMT Backend: move undefined memory behavior modelling to firrtl IR level (#2095)Kevin Laeufer
2020-09-30Handle case where rdata of mem RW port split to R+W ports drives another memAlbert Magyar
2020-09-16Change to Apache 2.0 License (#1901)Chick Markley
2020-08-21Fix Uniquify bug and improve ReplaceSeqMems transforms (#1855)Jack Koenig
2020-08-14All of src/ formatted with scalafmtchick
2020-08-13Remove LegacyAnnotation and [most] MoultingYaml (#1833)Jack Koenig
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
2020-07-29[2.13] replace `= Unit` with `= ()`Kevin Laeufer
2020-07-29MemConf: build list of tuples and turn it into a map at the endKevin Laeufer
2020-07-29[2.13] convert toSeq and toMap where necessary to compileKevin Laeufer
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
2020-03-11Migrate to DependencyAPISchuyler Eldridge
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
2020-02-12Support MemConfs with very deep memories (#1367)Jerry Zhao
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
2019-09-30Improve read-under-write parameter supportAlbert Magyar
2019-09-16Rename gender to flowSchuyler Eldridge
2019-08-01Followup to PR #1142chick
2019-07-08Remove some warnings (#1118)Leway Colin
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
2019-04-25Add FirrtlStage, make Driver compatibility layerSchuyler Eldridge
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-03-19Designs with no SeqMems should produce empty MemConf strings, and this should...John Wright
2019-03-07Add a data structure for memory conf reading and writing (#1041)John Wright
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