| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-09-16 | Change to Apache 2.0 License (#1901) | Chick Markley |
| 2020-08-14 | All of src/ formatted with scalafmt | chick |
| 2019-10-18 | Upstream intervals (#870) | Adam Izraelevitz |
| 2019-09-30 | Implement read-first memories in VerilogMemDelays | Albert Magyar |
| 2019-09-16 | Rename gender to flow | Schuyler Eldridge |
| 2019-06-18 | Use scalafix to remove unused import and deprecated procedure syntax (#1074) | Leway Colin |
| 2018-11-26 | Make return types of util functions more specific (#949) | Albert Magyar |
| 2018-03-19 | Masks for zero-width fields of mems should be width zero. (#763) | grebe |
| 2017-02-23 | move more general utils out of memutils, mov WIR helpers to WIR.scala and upd... | Angie |
| 2017-02-23 | messed up clocktype match | Angie |
| 2017-02-23 | added more helpers | Angie |
| 2017-01-27 | Fix signed types (#422) | Angie Wang |
| 2016-10-24 | match fromBits order with toBits, toBitMask (#349) | Donggyu |
| 2016-10-23 | Fix bitmask (#346) | Angie Wang |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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