diff options
| author | azidar | 2015-12-09 18:31:45 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | be78d49aa01c097978f69a3b022acb2047fdf438 (patch) | |
| tree | 76dc4b32b5e6861938404ebb4d124ca5b87d13a5 /test/features/ExModule.fir | |
| parent | c427b31a1ef8361b643d5f7435aeb42472dfe626 (diff) | |
New memory works with verilog. Slowly changing tests and fixing bugs.
Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables
Diffstat (limited to 'test/features/ExModule.fir')
| -rw-r--r-- | test/features/ExModule.fir | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir index 146d11b9..b31c77c9 100644 --- a/test/features/ExModule.fir +++ b/test/features/ExModule.fir @@ -3,9 +3,9 @@ circuit Top : module Top : output z : UInt<4> inst i of BlackBox - i.x := UInt(1) - i.y := UInt(2) - z := i.z + i.x <= UInt(1) + i.y <= UInt(2) + z <= i.z extmodule BlackBox : input x : UInt<4> input y : UInt<4> |