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| author | azidar | 2015-12-03 15:12:02 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | c427b31a1ef8361b643d5f7435aeb42472dfe626 (patch) | |
| tree | 6ae504ba1b37b9d0fef281b491cf932ac6826c7b /test/features/ExModule.fir | |
| parent | ece8ec00868c182e141e8d1ac75bfb60bfaa87ec (diff) | |
WIP. Compiles and almost done with verilog backend. Need to think about emitting ports (and the assignments to them)
Diffstat (limited to 'test/features/ExModule.fir')
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