From be78d49aa01c097978f69a3b022acb2047fdf438 Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 9 Dec 2015 18:31:45 -0800
Subject: New memory works with verilog. Slowly changing tests and fixing bugs.
 Decided to not have Conditionally in low firrtl - instead, Print and Stop
 have enables

---
 test/features/ExModule.fir | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'test/features/ExModule.fir')

diff --git a/test/features/ExModule.fir b/test/features/ExModule.fir
index 146d11b9..b31c77c9 100644
--- a/test/features/ExModule.fir
+++ b/test/features/ExModule.fir
@@ -3,9 +3,9 @@ circuit Top :
   module Top : 
     output z : UInt<4>
     inst i of BlackBox
-    i.x := UInt(1)
-    i.y := UInt(2)
-    z := i.z
+    i.x <= UInt(1)
+    i.y <= UInt(2)
+    z <= i.z
   extmodule BlackBox :
     input x : UInt<4>
     input y : UInt<4>
-- 
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