chiselX - Chisel with SFC compatibility

Age	Commit message (Collapse)	Author
2016-08-25	fix a bug in setModName	Donggyu Kim

2016-08-24	Per Chisel meeting.	chick
	signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR
2016-08-21	AnnotatingExample:	chick
	Removed extraneous logic Renamed doStuff to buildAnnotatedCircuit Removed println's
2016-08-21	Add AnnotationSpec file which provides an example of a way to implement ↵	chick
	generation of annotations in a chisel circuit that could be used by custom firrtl passes This spec also shows and tests in a limited way the new API of .signalName, .pathName, parentModName which allows access to the various path information of a chisel component (something that subclasses SignalId, most prominently SubClasses of Data and Module
2016-08-21	Add annotating example to test new signal name api	chick

2016-08-21	provides signal name methods for firrtl annotation and chisel testers	Donggyu Kim
	* signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent module(not instance) name.
2016-08-15	Make "def width" a private API; expose isWidthKnown instead (#257)	Andrew Waterman
	* Make "def width" a private API; expose isWidthKnown instead Resolves #256. Since width was used to determine whether getWidth would succeed, I added def isWidthKnown: Boolean but another option would be to expose something like def widthOption: Option[Int] ...thoughts? * Document getWidth/isWidthKnown * Add widthOption for more idiomatic Scala manipulation of widths
2016-08-09	Support Module name overrides with "override def desiredName"	Andrew Waterman
	The API allowed this before, but not safely, as users could create name conflicts. This exposes the pre-deduplication/sanitization naming API, and closes the other one.
2016-08-09	counter(inc,n) example should reflect actual use (#252)	Colin Schmidt

2016-07-31	Remove deprecated FileSystemUtilities	Andrew Waterman
	This has been deprecated for a long time now (and really shouldn't have existed to begin with).
2016-07-31	Fix two deprecation warnings	Andrew Waterman

2016-07-20	Generate better names for nodes (#190)	Jack Koenig
	For Chisel nodes defined in Module class-level values of type Option or Iterable, we can still use reflection to assign names based on the name of the value. This works for arbitrary nesting of Option and Iterable so long as the innermost type is HasId. Note that this excludes Maps which always have an innermost type of Tuple2[_,_].
2016-07-11	bitpat should keep the width of uint (#232)	Donggyu

2016-07-07	Don't check GCD result before sending it a request	Andrew Waterman

2016-07-07	Improve QoR for Log2	Andrew Waterman
	For reasonable circuit delay, need to divide & conquer.
2016-07-07	Improve Fill code generation	Andrew Waterman

2016-07-07	Correct erroneous Log2 documentation	Andrew Waterman

2016-07-07	Avoid needlessly creating Vecs	Andrew Waterman

2016-06-28	Merge branch 'master' into renamechisel3	Jim Lawson

2016-06-27	Guard firrtl stop, fixing pipelined reset	Andrew Waterman

2016-06-24	Merge branch 'master' into renamechisel3	Jim Lawson

2016-06-23	Expose FIRRTL stop construct	Andrew Waterman

2016-06-22	Merge branch 'master' into renamechisel3	Jim Lawson

2016-06-20	make sure MuxCase and MuxLookup can take all subclasses of Data (#222)	Howard Mao

2016-06-20	Rename "package", "import", and explicit references to "chisel3".	Jim Lawson

2016-06-20	Rename chisel3 package.	Jim Lawson

2016-06-08	Move deprecated debug into compatibility	ducky

2016-06-08	Package split chisel core	ducky

2016-06-08	Move chisel/... to chisel/core/..., make chisel/compatibility ↵	ducky
	package/folder, move more things into utils
2016-06-08	Move utils into utils	ducky

2016-06-08	Add implicit xToLiteral, add Element, use internal package object	ducky

2016-06-08	Rename Chisel -> chisel in tests	ducky

2016-06-08	Rename packages to lowercase chisel, add compatibility layer	ducky

2016-06-01	Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)	Wesley W. Terpstra
	* chiselTests: include an example of two empty Vectors killing FIRRTL * Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq In Chisel, two vectors are NOT equal just if their contents are equal. For example, two empty vectors should not be considered equal. This patch makes Vec use the HasId._id for equality like other Chisel types. Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate one of the named vectors and emit bad IR.
2016-05-31	Remove unsafe implicit conversions from BitPat	ducky

2016-05-31	Move BitPat out of core/frontend, add implicit conversion	Ducky

2016-05-26	Fix type constraint on PriorityMux	Andrew Waterman

2016-05-20	Merge pull request #186 from ucb-bar/sloc_impl	Richard Lin
	Source locators
2016-05-20	Implementation of source locators	ducky

2016-05-20	Update BackendCompilationUtilities.verilogToCpp to specify top-module	jackkoenig
	This prevents Verilator from erroring when it cannot determine the top-module. It also changes the PRINTF_COND guard to correctly use the top-level reset instead of just the top of the Chisel-generated code.
2016-05-12	remove Tester.scala because chiselMain is now implemented in the ↵	Danny
	chisel-testers repo
2016-05-11	RegNext and RegInit should match Reg(next=) and Reg(init=)	Andrew Waterman

2016-05-10	Move emit out of IR	ducky

2016-05-09	remove vpi source files	Donggyu Kim

2016-05-09	fix width inference in enum	Donggyu Kim

2016-05-09	get -> getOrElse	Donggyu Kim

2016-05-05	Move Chisel API into separate chiselFrontend compilation unit in preparation ↵	ducky
	for source locator macros
2016-05-04	Multiple assign tester	ducky
	Closes #90
2016-05-04	Remove dependences from Chisel core on Chisel utils	Andrew Waterman
	Partially resolves #164
2016-05-04	Support writing literals like 1.U or -1.S	Andrew Waterman