Remove dependences from Chisel core on Chisel utils

Partially resolves #164

6 files changed, 56 insertions, 39 deletions

diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index de685d0a..4d35e2f0 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -188,7 +188,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] {
 
   /** Outputs the number of elements for which p is true.
     */
-  def count(p: T => Bool): UInt = PopCount((this map p).toSeq)
+  def count(p: T => Bool): UInt = SeqUtils.count(this map p)
 
   /** Helper function that appends an index (literal value) to each element,
     * useful for hardware generators which output an index.
@@ -197,11 +197,11 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] {
 
   /** Outputs the index of the first element for which p outputs true.
     */
-  def indexWhere(p: T => Bool): UInt = PriorityMux(indexWhereHelper(p))
+  def indexWhere(p: T => Bool): UInt = SeqUtils.priorityMux(indexWhereHelper(p))
 
   /** Outputs the index of the last element for which p outputs true.
     */
-  def lastIndexWhere(p: T => Bool): UInt = PriorityMux(indexWhereHelper(p).reverse)
+  def lastIndexWhere(p: T => Bool): UInt = SeqUtils.priorityMux(indexWhereHelper(p).reverse)
 
   /** Outputs the index of the element for which p outputs true, assuming that
     * the there is exactly one such element.
@@ -213,7 +213,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] {
     * true is NOT checked (useful in cases where the condition doesn't always
     * hold, but the results are not used in those cases)
     */
-  def onlyIndexWhere(p: T => Bool): UInt = Mux1H(indexWhereHelper(p))
+  def onlyIndexWhere(p: T => Bool): UInt = SeqUtils.oneHotMux(indexWhereHelper(p))
 }
 
 /** Base class for data types defined as a bundle of other data types.
diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index 3fa3dc20..8879491c 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -110,7 +110,7 @@ abstract class Data(dirArg: Direction) extends HasId {
     *
     * This performs the inverse operation of fromBits(Bits).
     */
-  def toBits(): UInt = Cat(this.flatten.reverse)
+  def toBits(): UInt = SeqUtils.asUInt(this.flatten)
 }
 
 object Wire {
diff --git a/src/main/scala/Chisel/SeqUtils.scala b/src/main/scala/Chisel/SeqUtils.scala
new file mode 100644
index 00000000..c63f5735
--- /dev/null
+++ b/src/main/scala/Chisel/SeqUtils.scala
@@ -0,0 +1,47 @@
+// See LICENSE for license details.
+
+package Chisel
+
+private[Chisel] object SeqUtils {
+  /** Equivalent to Cat(r(n-1), ..., r(0)) */
+  def asUInt[T <: Bits](in: Seq[T]): UInt = {
+    if (in.tail.isEmpty) {
+      in.head.asUInt
+    } else {
+      val left = asUInt(in.slice(0, in.length/2))
+      val right = asUInt(in.slice(in.length/2, in.length))
+      right ## left
+    }
+  }
+
+  /** Counts the number of true Bools in a Seq */
+  def count(in: Seq[Bool]): UInt = {
+    if (in.size == 0) {
+      UInt(0)
+    } else if (in.size == 1) {
+      in.head
+    } else {
+      count(in.slice(0, in.size/2)) + (UInt(0) ## count(in.slice(in.size/2, in.size)))
+    }
+  }
+
+  /** Returns data value corresponding to first true predicate */
+  def priorityMux[T <: Bits](in: Seq[(Bool, T)]): T = {
+    if (in.size == 1) {
+      in.head._2
+    } else {
+      Mux(in.head._1, in.head._2, priorityMux(in.tail))
+    }
+  }
+
+  /** Returns data value corresponding to lone true predicate */
+  def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = {
+    if (in.tail.isEmpty) {
+      in.head._2
+    } else {
+      val masked = for ((s, i) <- in) yield Mux(s, i.toBits, Bits(0))
+      val width = in.map(_._2.width).reduce(_ max _)
+      in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
+    }
+  }
+}
diff --git a/src/main/scala/Chisel/util/Bitwise.scala b/src/main/scala/Chisel/util/Bitwise.scala
index 7188ec32..239a295e 100644
--- a/src/main/scala/Chisel/util/Bitwise.scala
+++ b/src/main/scala/Chisel/util/Bitwise.scala
@@ -15,15 +15,7 @@ object FillInterleaved
   */
 object PopCount
 {
-  def apply(in: Iterable[Bool]): UInt = {
-    if (in.size == 0) {
-      UInt(0)
-    } else if (in.size == 1) {
-      in.head
-    } else {
-      apply(in.slice(0, in.size/2)) + Cat(UInt(0), apply(in.slice(in.size/2, in.size)))
-    }
-  }
+  def apply(in: Iterable[Bool]): UInt = SeqUtils.count(in.toSeq)
   def apply(in: Bits): UInt = apply((0 until in.getWidth).map(in(_)))
 }
 
diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/Chisel/util/Cat.scala
index 088a208e..dd706e62 100644
--- a/src/main/scala/Chisel/util/Cat.scala
+++ b/src/main/scala/Chisel/util/Cat.scala
@@ -14,13 +14,5 @@ object Cat {
     * @param r any number of other Data elements to be combined in order
     * @return A UInt which is all of the bits combined together
     */
-  def apply[T <: Bits](r: Seq[T]): UInt = {
-    if (r.tail.isEmpty) {
-      r.head.asUInt
-    } else {
-      val left = apply(r.slice(0, r.length/2))
-      val right = apply(r.slice(r.length/2, r.length))
-      left ## right
-    }
-  }
+  def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse)
 }
diff --git a/src/main/scala/Chisel/util/Mux.scala b/src/main/scala/Chisel/util/Mux.scala
index c2833103..a7d835f6 100644
--- a/src/main/scala/Chisel/util/Mux.scala
+++ b/src/main/scala/Chisel/util/Mux.scala
@@ -12,15 +12,7 @@ object Mux1H
 {
   def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T =
     apply(sel zip in)
-  def apply[T <: Data](in: Iterable[(Bool, T)]): T = {
-    if (in.tail.isEmpty) {
-      in.head._2
-    } else {
-      val masked = in map {case (s, i) => Mux(s, i.toBits, Bits(0))}
-      val width = in.map(_._2.width).reduce(_ max _)
-      in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
-    }
-  }
+  def apply[T <: Data](in: Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in)
   def apply[T <: Data](sel: UInt, in: Seq[T]): T =
     apply((0 until in.size).map(sel(_)), in)
   def apply(sel: UInt, in: UInt): Bool = (sel & in).orR
@@ -33,13 +25,7 @@ object Mux1H
   */
 object PriorityMux
 {
-  def apply[T <: Bits](in: Seq[(Bool, T)]): T = {
-    if (in.size == 1) {
-      in.head._2
-    } else {
-      Mux(in.head._1, in.head._2, apply(in.tail))
-    }
-  }
+  def apply[T <: Bits](in: Seq[(Bool, T)]): T = SeqUtils.priorityMux(in)
   def apply[T <: Bits](sel: Seq[Bool], in: Seq[T]): T = apply(sel zip in)
   def apply[T <: Bits](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in)
 }