Package split chisel core

5 files changed, 101 insertions, 48 deletions

diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala
index 6e72cdd3..54cf033d 100644
--- a/src/main/scala/chisel/compatibility.scala
+++ b/src/main/scala/chisel/compatibility.scala
@@ -4,54 +4,54 @@
 // moving to the more standard package naming convention chisel (lowercase c).
 
 package object Chisel {
-  type Direction = chisel.Direction
-  val INPUT = chisel.INPUT
-  val OUTPUT = chisel.OUTPUT
-  val NO_DIR = chisel.NO_DIR
-  val debug = chisel.debug
-  type Flipped = chisel.Flipped
-  type Data = chisel.Data
-  val Wire = chisel.Wire
-  val Clock = chisel.Clock
-  type Clock = chisel.Clock
-
-  type Aggregate = chisel.Aggregate
-  val Vec = chisel.Vec
-  type Vec[T <: Data] = chisel.Vec[T]
-  type VecLike[T <: Data] = chisel.VecLike[T]
-  type Bundle = chisel.Bundle
-
-  val assert = chisel.assert
-
-  type Element = chisel.Element
-  type Bits = chisel.Bits
-  val Bits = chisel.Bits
-  type Num[T <: Data] = chisel.Num[T]
-  type UInt = chisel.UInt
-  val UInt = chisel.UInt
-  type SInt = chisel.SInt
-  val SInt = chisel.SInt
-  type Bool = chisel.Bool
-  val Bool = chisel.Bool
-  val Mux = chisel.Mux
-
-  type BlackBox = chisel.BlackBox
-
-  val Mem = chisel.Mem
-  type MemBase[T <: Data] = chisel.MemBase[T]
-  type Mem[T <: Data] = chisel.Mem[T]
-  val SeqMem = chisel.SeqMem
-  type SeqMem[T <: Data] = chisel.SeqMem[T]
-
-  val Module = chisel.Module
-  type Module = chisel.Module
-
-  val printf = chisel.printf
-
-  val Reg = chisel.Reg
-
-  val when = chisel.when
-  type WhenContext = chisel.WhenContext
+  type Direction = chisel.core.Direction
+  val INPUT = chisel.core.INPUT
+  val OUTPUT = chisel.core.OUTPUT
+  val NO_DIR = chisel.core.NO_DIR
+  val debug = chisel.core.debug
+  type Flipped = chisel.core.Flipped
+  type Data = chisel.core.Data
+  val Wire = chisel.core.Wire
+  val Clock = chisel.core.Clock
+  type Clock = chisel.core.Clock
+
+  type Aggregate = chisel.core.Aggregate
+  val Vec = chisel.core.Vec
+  type Vec[T <: Data] = chisel.core.Vec[T]
+  type VecLike[T <: Data] = chisel.core.VecLike[T]
+  type Bundle = chisel.core.Bundle
+
+  val assert = chisel.core.assert
+
+  type Element = chisel.core.Element
+  type Bits = chisel.core.Bits
+  val Bits = chisel.core.Bits
+  type Num[T <: Data] = chisel.core.Num[T]
+  type UInt = chisel.core.UInt
+  val UInt = chisel.core.UInt
+  type SInt = chisel.core.SInt
+  val SInt = chisel.core.SInt
+  type Bool = chisel.core.Bool
+  val Bool = chisel.core.Bool
+  val Mux = chisel.core.Mux
+
+  type BlackBox = chisel.core.BlackBox
+
+  val Mem = chisel.core.Mem
+  type MemBase[T <: Data] = chisel.core.MemBase[T]
+  type Mem[T <: Data] = chisel.core.Mem[T]
+  val SeqMem = chisel.core.SeqMem
+  type SeqMem[T <: Data] = chisel.core.SeqMem[T]
+
+  val Module = chisel.core.Module
+  type Module = chisel.core.Module
+
+  val printf = chisel.core.printf
+
+  val Reg = chisel.core.Reg
+
+  val when = chisel.core.when
+  type WhenContext = chisel.core.WhenContext
 
 
   type BackendCompilationUtilities = chisel.BackendCompilationUtilities
diff --git a/src/main/scala/chisel/package.scala b/src/main/scala/chisel/package.scala
index b6036c75..f7ed6b13 100644
--- a/src/main/scala/chisel/package.scala
+++ b/src/main/scala/chisel/package.scala
@@ -5,6 +5,56 @@ package object chisel {
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   import util.BitPat
 
+
+  type Direction = chisel.core.Direction
+  val INPUT = chisel.core.INPUT
+  val OUTPUT = chisel.core.OUTPUT
+  val NO_DIR = chisel.core.NO_DIR
+  type Flipped = chisel.core.Flipped
+  type Data = chisel.core.Data
+  val Wire = chisel.core.Wire
+  val Clock = chisel.core.Clock
+  type Clock = chisel.core.Clock
+
+  type Aggregate = chisel.core.Aggregate
+  val Vec = chisel.core.Vec
+  type Vec[T <: Data] = chisel.core.Vec[T]
+  type VecLike[T <: Data] = chisel.core.VecLike[T]
+  type Bundle = chisel.core.Bundle
+
+  val assert = chisel.core.assert
+
+  type Element = chisel.core.Element
+  type Bits = chisel.core.Bits
+  val Bits = chisel.core.Bits
+  type Num[T <: Data] = chisel.core.Num[T]
+  type UInt = chisel.core.UInt
+  val UInt = chisel.core.UInt
+  type SInt = chisel.core.SInt
+  val SInt = chisel.core.SInt
+  type Bool = chisel.core.Bool
+  val Bool = chisel.core.Bool
+  val Mux = chisel.core.Mux
+
+  type BlackBox = chisel.core.BlackBox
+
+  val Mem = chisel.core.Mem
+  type MemBase[T <: Data] = chisel.core.MemBase[T]
+  type Mem[T <: Data] = chisel.core.Mem[T]
+  val SeqMem = chisel.core.SeqMem
+  type SeqMem[T <: Data] = chisel.core.SeqMem[T]
+
+  val Module = chisel.core.Module
+  type Module = chisel.core.Module
+
+  val printf = chisel.core.printf
+
+  val Reg = chisel.core.Reg
+
+  val when = chisel.core.when
+  type WhenContext = chisel.core.WhenContext
+
+
   implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
     def U: UInt = UInt(x, Width())
     def S: SInt = SInt(x, Width())
diff --git a/src/main/scala/chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala
index 94413fc7..d7d62ea3 100644
--- a/src/main/scala/chisel/util/Bitwise.scala
+++ b/src/main/scala/chisel/util/Bitwise.scala
@@ -6,6 +6,7 @@
 package chisel.util
 
 import chisel._
+import chisel.core.SeqUtils
 
 object FillInterleaved
 {
diff --git a/src/main/scala/chisel/util/Cat.scala b/src/main/scala/chisel/util/Cat.scala
index 5b3c613e..b47da706 100644
--- a/src/main/scala/chisel/util/Cat.scala
+++ b/src/main/scala/chisel/util/Cat.scala
@@ -3,6 +3,7 @@
 package chisel.util
 
 import chisel._
+import chisel.core.SeqUtils
 
 object Cat {
   /** Combine data elements together
diff --git a/src/main/scala/chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala
index cfff4485..6f074a7e 100644
--- a/src/main/scala/chisel/util/Mux.scala
+++ b/src/main/scala/chisel/util/Mux.scala
@@ -6,6 +6,7 @@
 package chisel.util
 
 import chisel._
+import chisel.core.SeqUtils
 
 /** Builds a Mux tree out of the input signal vector using a one hot encoded
   select signal. Returns the output of the Mux tree.