Rename packages to lowercase chisel, add compatibility layer

27 files changed, 180 insertions, 38 deletions

diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/Chisel/BitPat.scala
index 96206f63..a6833ed2 100644
--- a/src/main/scala/Chisel/BitPat.scala
+++ b/src/main/scala/Chisel/BitPat.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.language.experimental.macros
 
-import Chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
 object BitPat {
   /** Parses a bit pattern string into (bits, mask, width).
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/chisel/Driver.scala
index 02204684..ba2b1389 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/chisel/Driver.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.sys.process._
 import java.io._
diff --git a/src/main/scala/Chisel/FileSystemUtilities.scala b/src/main/scala/chisel/FileSystemUtilities.scala
index 575ae138..f100eaf6 100644
--- a/src/main/scala/Chisel/FileSystemUtilities.scala
+++ b/src/main/scala/chisel/FileSystemUtilities.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 @deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0")
 trait FileSystemUtilities {
diff --git a/src/main/scala/Chisel/ImplicitConversions.scala b/src/main/scala/chisel/ImplicitConversions.scala
index 6a230022..f786d4f1 100644
--- a/src/main/scala/Chisel/ImplicitConversions.scala
+++ b/src/main/scala/chisel/ImplicitConversions.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 object ImplicitConversions {
   implicit def intToUInt(x: Int): UInt = UInt(x)
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/chisel/Main.scala
index a72debc3..79e5c9ca 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/chisel/Main.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import java.io.File
 
diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala
new file mode 100644
index 00000000..80936a42
--- /dev/null
+++ b/src/main/scala/chisel/compatibility.scala
@@ -0,0 +1,139 @@
+// See LICENSE for license details.
+
+// Allows legacy users to continue using Chisel (capital C) package name while
+// moving to the more standard package naming convention chisel (lowercase c).
+
+package object Chisel {
+  type Direction = chisel.Direction
+  val INPUT = chisel.INPUT
+  val OUTPUT = chisel.OUTPUT
+  val NO_DIR = chisel.NO_DIR
+  val debug = chisel.debug
+  type Flipped = chisel.Flipped
+  type Data = chisel.Data
+  val Wire = chisel.Wire
+  val Clock = chisel.Clock
+  type Clock = chisel.Clock
+
+  type Aggregate = chisel.Aggregate
+  val Vec = chisel.Vec
+  type Vec[T <: Data] = chisel.Vec[T]
+  type VecLike[T <: Data] = chisel.VecLike[T]
+  type Bundle = chisel.Bundle
+
+  val assert = chisel.assert
+
+  val BitPat = chisel.BitPat
+  type BitPat = chisel.BitPat
+
+  type Bits = chisel.Bits
+  val Bits = chisel.Bits
+  type Num[T <: Data] = chisel.Num[T]
+  type UInt = chisel.UInt
+  val UInt = chisel.UInt
+  type SInt = chisel.SInt
+  val SInt = chisel.SInt
+  type Bool = chisel.Bool
+  val Bool = chisel.Bool
+  val Mux = chisel.Mux
+
+  type BlackBox = chisel.BlackBox
+
+  val Mem = chisel.Mem
+  type MemBase[T <: Data] = chisel.MemBase[T]
+  type Mem[T <: Data] = chisel.Mem[T]
+  val SeqMem = chisel.SeqMem
+  type SeqMem[T <: Data] = chisel.SeqMem[T]
+
+  val Module = chisel.Module
+  type Module = chisel.Module
+
+  val printf = chisel.printf
+
+  val Reg = chisel.Reg
+
+  val when = chisel.when
+  type WhenContext = chisel.WhenContext
+
+
+  type BackendCompilationUtilities = chisel.BackendCompilationUtilities
+  val Driver = chisel.Driver
+  type FileSystemUtilities = chisel.FileSystemUtilities
+  val ImplicitConversions = chisel.ImplicitConversions
+  val chiselMain = chisel.chiselMain
+  val throwException = chisel.throwException
+
+
+  val log2Up = chisel.log2Up
+  val log2Ceil = chisel.log2Ceil
+  val log2Down = chisel.log2Down
+  val log2Floor = chisel.log2Floor
+  val isPow2 = chisel.isPow2
+
+  type ArbiterIO[T <: Data] = chisel.ArbiterIO[T]
+  type LockingArbiterLike[T <: Data] = chisel.LockingArbiterLike[T]
+  type LockingRRArbiter[T <: Data] = chisel.LockingRRArbiter[T]
+  type LockingArbiter[T <: Data] = chisel.LockingArbiter[T]
+  type RRArbiter[T <: Data] = chisel.RRArbiter[T]
+  type Arbiter[T <: Data] = chisel.Arbiter[T]
+
+  val FillInterleaved = chisel.FillInterleaved
+  val PopCount = chisel.PopCount
+  val Fill = chisel.Fill
+  val Reverse = chisel.Reverse
+
+  val Cat = chisel.Cat
+
+  val Log2 = chisel.Log2
+
+  val unless = chisel.unless
+  type SwitchContext[T <: Bits] = chisel.SwitchContext[T]
+  val is = chisel.is
+  val switch = chisel.switch
+
+  type Counter = chisel.Counter
+  val Counter = chisel.Counter
+
+  type DecoupledIO[+T <: Data] = chisel.DecoupledIO[T]
+  val Decoupled = chisel.Decoupled
+  type EnqIO[T <: Data] = chisel.EnqIO[T]
+  type DeqIO[T <: Data] = chisel.DeqIO[T]
+  type DecoupledIOC[+T <: Data] = chisel.DecoupledIOC[T]
+  type QueueIO[T <: Data] = chisel.QueueIO[T]
+  type Queue[T <: Data] = chisel.Queue[T]
+  val Queue = chisel.Queue
+
+  val Enum = chisel.Enum
+
+  val LFSR16 = chisel.LFSR16
+
+  val ListLookup = chisel.ListLookup
+  val Lookup = chisel.Lookup
+
+  val Mux1H = chisel.Mux1H
+  val PriorityMux = chisel.PriorityMux
+  val MuxLookup = chisel.MuxLookup
+  val MuxCase = chisel.MuxCase
+
+  val OHToUInt = chisel.OHToUInt
+  val PriorityEncoder = chisel.PriorityEncoder
+  val UIntToOH = chisel.UIntToOH
+  val PriorityEncoderOH = chisel.PriorityEncoderOH
+
+  val RegNext = chisel.RegNext
+  val RegInit = chisel.RegInit
+  val RegEnable = chisel.RegEnable
+  val ShiftRegister = chisel.ShiftRegister
+
+  type ValidIO[+T <: Data] = chisel.ValidIO[T]
+  val Valid = chisel.Valid
+  val Pipe = chisel.Pipe
+  type Pipe[T <: Data] = chisel.Pipe[T]
+}
+
+package Chisel {
+  package object testers {
+    type BasicTester = chisel.testers.BasicTester
+    val TesterDriver = chisel.testers.TesterDriver
+  }
+}
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/chisel/internal/firrtl/Emitter.scala
index 7ca3268a..e48eb226 100644
--- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel/internal/firrtl/Emitter.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
+package chisel.internal.firrtl
+import chisel._
+import chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
 
-private[Chisel] object Emitter {
+private[chisel] object Emitter {
   def emit(circuit: Circuit): String = new Emitter(circuit).toString
 }
 
diff --git a/src/main/scala/Chisel/package.scala b/src/main/scala/chisel/package.scala
index f05e8b5d..1abbc74f 100644
--- a/src/main/scala/Chisel/package.scala
+++ b/src/main/scala/chisel/package.scala
@@ -1,9 +1,9 @@
-package object Chisel {
+package object chisel {
   import scala.language.experimental.macros
-  
+
   import internal.firrtl.Width
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-  
+
   implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
     def U: UInt = UInt(x, Width())
     def S: SInt = SInt(x, Width())
@@ -18,12 +18,12 @@ package object Chisel {
   implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
     def B: Bool = Bool(x)
   }
-  
+
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-  
+
     def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x
     def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
     def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/chisel/testers/BasicTester.scala
index b8c1494a..36ff7c52 100644
--- a/src/main/scala/Chisel/testers/BasicTester.scala
+++ b/src/main/scala/chisel/testers/BasicTester.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 
-package Chisel.testers
-import Chisel._
+package chisel.testers
+import chisel._
 
 import scala.language.experimental.macros
 
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/chisel/testers/TesterDriver.scala
index a56bb8b7..5c0275e0 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/chisel/testers/TesterDriver.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel.testers
-import Chisel._
+package chisel.testers
+
+import chisel._
 import scala.io.Source
 import scala.sys.process._
 import java.io._
diff --git a/src/main/scala/Chisel/throwException.scala b/src/main/scala/chisel/throwException.scala
index 702884aa..fdd62c7e 100644
--- a/src/main/scala/Chisel/throwException.scala
+++ b/src/main/scala/chisel/throwException.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 @deprecated("throwException doesn't exist in Chisel3", "3.0.0")
 @throws(classOf[Exception])
diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/chisel/util/Arbiter.scala
index 16ae9be5..afe48963 100644
--- a/src/main/scala/Chisel/util/Arbiter.scala
+++ b/src/main/scala/chisel/util/Arbiter.scala
@@ -3,7 +3,7 @@
 /** Arbiters in all shapes and sizes.
   */
 
-package Chisel
+package chisel
 
 /** An I/O bundle for the Arbiter */
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
diff --git a/src/main/scala/Chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala
index 239a295e..27064059 100644
--- a/src/main/scala/Chisel/util/Bitwise.scala
+++ b/src/main/scala/chisel/util/Bitwise.scala
@@ -3,7 +3,7 @@
 /** Miscellaneous circuit generators operating on bits.
   */
 
-package Chisel
+package chisel
 
 object FillInterleaved
 {
diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/chisel/util/Cat.scala
index dd706e62..a35619df 100644
--- a/src/main/scala/Chisel/util/Cat.scala
+++ b/src/main/scala/chisel/util/Cat.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 object Cat {
   /** Combine data elements together
diff --git a/src/main/scala/Chisel/util/CircuitMath.scala b/src/main/scala/chisel/util/CircuitMath.scala
index 06cab903..001be802 100644
--- a/src/main/scala/Chisel/util/CircuitMath.scala
+++ b/src/main/scala/chisel/util/CircuitMath.scala
@@ -3,7 +3,7 @@
 /** Circuit-land math operations.
   */
 
-package Chisel
+package chisel
 
 /** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
   * An alternative interpretation is it computes the minimum number of bits needed to represent x
diff --git a/src/main/scala/Chisel/util/Conditional.scala b/src/main/scala/chisel/util/Conditional.scala
index 9cab25ef..94f00080 100644
--- a/src/main/scala/Chisel/util/Conditional.scala
+++ b/src/main/scala/chisel/util/Conditional.scala
@@ -3,7 +3,7 @@
 /** Conditional blocks.
   */
 
-package Chisel
+package chisel
 
 import scala.language.reflectiveCalls
 import scala.language.experimental.macros
@@ -59,7 +59,9 @@ object switch {  // scalastyle:ignore object.name
   def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
     val sc = c.universe.internal.reificationSupport.freshTermName("sc")
     def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
-      case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      // TODO: remove when Chisel compatibility package is removed
+      case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      case q"chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
       case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
     }
     val q"..$body" = x
diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/chisel/util/Counter.scala
index 872e830a..dde1e347 100644
--- a/src/main/scala/Chisel/util/Counter.scala
+++ b/src/main/scala/chisel/util/Counter.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 /** A counter module
   * @param n number of counts before the counter resets (or one more than the
diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/chisel/util/Decoupled.scala
index 8e045855..955b0870 100644
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ b/src/main/scala/chisel/util/Decoupled.scala
@@ -3,7 +3,7 @@
 /** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them.
   */
 
-package Chisel
+package chisel
 
 /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
 class DecoupledIO[+T <: Data](gen: T) extends Bundle
@@ -108,7 +108,7 @@ class Queue[T <: Data](gen: T, val entries: Int,
 extends Module(override_reset=override_reset) {
   def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) =
     this(gen, entries, pipe, flow, Some(_reset))
-  
+
   val io = new QueueIO(gen, entries)
 
   val ram = Mem(entries, gen)
diff --git a/src/main/scala/Chisel/util/Enum.scala b/src/main/scala/chisel/util/Enum.scala
index 20057197..2757a06c 100644
--- a/src/main/scala/Chisel/util/Enum.scala
+++ b/src/main/scala/chisel/util/Enum.scala
@@ -3,7 +3,7 @@
 /** Enum generators, allowing circuit constants to have more meaningful names.
   */
 
-package Chisel
+package chisel
 
 object Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
diff --git a/src/main/scala/Chisel/util/LFSR.scala b/src/main/scala/chisel/util/LFSR.scala
index 839b1d1f..1befb8ca 100644
--- a/src/main/scala/Chisel/util/LFSR.scala
+++ b/src/main/scala/chisel/util/LFSR.scala
@@ -3,7 +3,7 @@
 /** LFSRs in all shapes and sizes.
   */
 
-package Chisel
+package chisel
 
 // scalastyle:off magic.number
 /** linear feedback shift register
diff --git a/src/main/scala/Chisel/util/Lookup.scala b/src/main/scala/chisel/util/Lookup.scala
index 54922fc4..1fdfd6ae 100644
--- a/src/main/scala/Chisel/util/Lookup.scala
+++ b/src/main/scala/chisel/util/Lookup.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 object ListLookup {
   def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
diff --git a/src/main/scala/Chisel/util/Math.scala b/src/main/scala/chisel/util/Math.scala
index 5f8212d8..1bf667ce 100644
--- a/src/main/scala/Chisel/util/Math.scala
+++ b/src/main/scala/chisel/util/Math.scala
@@ -3,7 +3,7 @@
 /** Scala-land math helper functions, like logs.
   */
 
-package Chisel
+package chisel
 
 /** Compute the log2 rounded up with min value of 1 */
 object log2Up {
diff --git a/src/main/scala/Chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala
index 9d92321a..97467240 100644
--- a/src/main/scala/Chisel/util/Mux.scala
+++ b/src/main/scala/chisel/util/Mux.scala
@@ -3,7 +3,7 @@
 /** Mux circuit generators.
   */
 
-package Chisel
+package chisel
 
 /** Builds a Mux tree out of the input signal vector using a one hot encoded
   select signal. Returns the output of the Mux tree.
diff --git a/src/main/scala/Chisel/util/OneHot.scala b/src/main/scala/chisel/util/OneHot.scala
index 73f27403..5d1de1a7 100644
--- a/src/main/scala/Chisel/util/OneHot.scala
+++ b/src/main/scala/chisel/util/OneHot.scala
@@ -3,7 +3,7 @@
 /** Circuit generators for working with one-hot representations.
   */
 
-package Chisel
+package chisel
 
 /** Converts from One Hot Encoding to a UInt indicating which bit is active
   * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
diff --git a/src/main/scala/Chisel/util/Reg.scala b/src/main/scala/chisel/util/Reg.scala
index 6584a4bf..1808af76 100644
--- a/src/main/scala/Chisel/util/Reg.scala
+++ b/src/main/scala/chisel/util/Reg.scala
@@ -3,7 +3,7 @@
 /** Variations and helpers for registers.
   */
 
-package Chisel
+package chisel
 
 object RegNext {
 
diff --git a/src/main/scala/Chisel/util/TransitName.scala b/src/main/scala/chisel/util/TransitName.scala
index ec5a11cc..141b10bc 100644
--- a/src/main/scala/Chisel/util/TransitName.scala
+++ b/src/main/scala/chisel/util/TransitName.scala
@@ -1,4 +1,4 @@
-package Chisel
+package chisel
 
 import internal.HasId
 
diff --git a/src/main/scala/Chisel/util/Valid.scala b/src/main/scala/chisel/util/Valid.scala
index 9e2202bb..cffed0a7 100644
--- a/src/main/scala/Chisel/util/Valid.scala
+++ b/src/main/scala/chisel/util/Valid.scala
@@ -3,7 +3,7 @@
 /** Wrappers for valid interfaces and associated circuit generators using them.
   */
 
-package Chisel
+package chisel
 
 /** An I/O Bundle containing data and a signal determining if it is valid */
 class ValidIO[+T <: Data](gen2: T) extends Bundle