Rename packages to lowercase chisel, add compatibility layer

43 files changed, 277 insertions, 134 deletions

diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/chisel/Aggregate.scala
index 1eef5d69..4f3f3de0 100644
--- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel/Aggregate.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashSet, LinkedHashMap}
@@ -15,7 +15,7 @@ import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, Sour
   * of) other Data objects.
   */
 sealed abstract class Aggregate(dirArg: Direction) extends Data(dirArg) {
-  private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[chisel] def cloneTypeWidth(width: Width): this.type = cloneType
   def width: Width = flatten.map(_.width).reduce(_ + _)
 }
 
@@ -163,8 +163,8 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
     Vec(length, gen).asInstanceOf[this.type]
 
   private val t = gen
-  private[Chisel] def toType: String = s"${t.toType}[$length]"
-  private[Chisel] lazy val flatten: IndexedSeq[Bits] =
+  private[chisel] def toType: String = s"${t.toType}[$length]"
+  private[chisel] lazy val flatten: IndexedSeq[Bits] =
     (0 until length).flatMap(i => this.apply(i).flatten)
 
   for ((elt, i) <- self zipWithIndex)
@@ -315,7 +315,7 @@ class Bundle extends Aggregate(NO_DIR) {
 
   /** Returns a list of elements in this Bundle.
     */
-  private[Chisel] lazy val namedElts = {
+  private[chisel] lazy val namedElts = {
     val nameMap = LinkedHashMap[String, Data]()
     val seen = HashSet[Data]()
     for (m <- getClass.getMethods.sortWith(_.getName < _.getName)) {
@@ -331,17 +331,17 @@ class Bundle extends Aggregate(NO_DIR) {
     }
     ArrayBuffer(nameMap.toSeq:_*) sortWith {case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn))}
   }
-  private[Chisel] def toType = {
+  private[chisel] def toType = {
     def eltPort(elt: Data): String = {
       val flipStr = if (elt.isFlip) "flip " else ""
       s"${flipStr}${elt.getRef.name} : ${elt.toType}"
     }
     s"{${namedElts.reverse.map(e => eltPort(e._2)).mkString(", ")}}"
   }
-  private[Chisel] lazy val flatten = namedElts.flatMap(_._2.flatten)
-  private[Chisel] def addElt(name: String, elt: Data): Unit =
+  private[chisel] lazy val flatten = namedElts.flatMap(_._2.flatten)
+  private[chisel] def addElt(name: String, elt: Data): Unit =
     namedElts += name -> elt
-  private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name
+  private[chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
 
   override def cloneType : this.type = {
@@ -372,6 +372,6 @@ class Bundle extends Aggregate(NO_DIR) {
   }
 }
 
-private[Chisel] object Bundle {
+private[chisel] object Bundle {
   val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits")
 }
diff --git a/chiselFrontend/src/main/scala/Chisel/Assert.scala b/chiselFrontend/src/main/scala/chisel/Assert.scala
index c086f014..0d660bc3 100644
--- a/chiselFrontend/src/main/scala/Chisel/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel/Assert.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.reflect.macros.blackbox.Context
 import scala.language.experimental.macros
diff --git a/chiselFrontend/src/main/scala/Chisel/Bits.scala b/chiselFrontend/src/main/scala/chisel/Bits.scala
index bc8cc8e2..8ec7c1b9 100644
--- a/chiselFrontend/src/main/scala/Chisel/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel/Bits.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.language.experimental.macros
 
@@ -25,9 +25,9 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   // Arguments for: self-checking code (can't do arithmetic on bits)
   // Arguments against: generates down to a FIRRTL UInt anyways
 
-  private[Chisel] def fromInt(x: BigInt, w: Int): this.type
+  private[chisel] def fromInt(x: BigInt, w: Int): this.type
 
-  private[Chisel] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
+  private[chisel] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
 
   def cloneType: this.type = cloneTypeWidth(width)
 
@@ -118,16 +118,16 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg:
   final def do_apply(x: BigInt, y: BigInt)(implicit sourceInfo: SourceInfo): UInt =
     apply(x.toInt, y.toInt)
 
-  private[Chisel] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T =
+  private[chisel] def unop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref))
-  private[Chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T =
+  private[chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: BigInt): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, ILit(other)))
-  private[Chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T =
+  private[chisel] def binop[T <: Data](sourceInfo: SourceInfo, dest: T, op: PrimOp, other: Bits): T =
     pushOp(DefPrim(sourceInfo, dest, op, this.ref, other.ref))
 
-  private[Chisel] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool =
+  private[chisel] def compop(sourceInfo: SourceInfo, op: PrimOp, other: Bits): Bool =
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref))
-  private[Chisel] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool =
+  private[chisel] def redop(sourceInfo: SourceInfo, op: PrimOp): Bool =
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref))
 
   /** Returns this wire zero padded up to the specified width.
@@ -356,13 +356,13 @@ abstract trait Num[T <: Data] {
 /** A data type for unsigned integers, represented as a binary bitvector.
   * Defines arithmetic operations between other integer types.
   */
-sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULit] = None)
+sealed class UInt private[chisel] (dir: Direction, width: Width, lit: Option[ULit] = None)
     extends Bits(dir, width, lit) with Num[UInt] {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type =
+  private[chisel] override def cloneTypeWidth(w: Width): this.type =
     new UInt(dir, w).asInstanceOf[this.type]
-  private[Chisel] def toType = s"UInt$width"
+  private[chisel] def toType = s"UInt$width"
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type =
+  override private[chisel] def fromInt(value: BigInt, width: Int): this.type =
     UInt(value, width).asInstanceOf[this.type]
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
@@ -482,7 +482,7 @@ sealed class UInt private[Chisel] (dir: Direction, width: Width, lit: Option[ULi
 }
 
 // This is currently a factory because both Bits and UInt inherit it.
-private[Chisel] sealed trait UIntFactory {
+private[chisel] sealed trait UIntFactory {
   /** Create a UInt type with inferred width. */
   def apply(): UInt = apply(NO_DIR, Width())
   /** Create a UInt type or port with fixed width. */
@@ -535,16 +535,16 @@ object UInt extends UIntFactory
 
 sealed class SInt private (dir: Direction, width: Width, lit: Option[SLit] = None)
     extends Bits(dir, width, lit) with Num[SInt] {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type =
+  private[chisel] override def cloneTypeWidth(w: Width): this.type =
     new SInt(dir, w).asInstanceOf[this.type]
-  private[Chisel] def toType = s"SInt$width"
+  private[chisel] def toType = s"SInt$width"
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
     case _: SInt => this connect that
     case _ => this badConnect that
   }
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type =
+  override private[chisel] def fromInt(value: BigInt, width: Int): this.type =
     SInt(value, width).asInstanceOf[this.type]
 
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
@@ -666,12 +666,12 @@ object SInt {
 /** A data type for booleans, defined as a single bit indicating true or false.
   */
 sealed class Bool(dir: Direction, lit: Option[ULit] = None) extends UInt(dir, Width(1), lit) {
-  private[Chisel] override def cloneTypeWidth(w: Width): this.type = {
+  private[chisel] override def cloneTypeWidth(w: Width): this.type = {
     require(!w.known || w.get == 1)
     new Bool(dir).asInstanceOf[this.type]
   }
 
-  override private[Chisel] def fromInt(value: BigInt, width: Int): this.type = {
+  override private[chisel] def fromInt(value: BigInt, width: Int): this.type = {
     require((value == 0 || value == 1) && width == 1)
     Bool(value == 1).asInstanceOf[this.type]
   }
diff --git a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala b/chiselFrontend/src/main/scala/chisel/BlackBox.scala
index b634f021..1dabc18f 100644
--- a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel/BlackBox.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import internal.Builder.pushCommand
 import internal.firrtl.{ModuleIO, DefInvalid}
@@ -24,10 +24,10 @@ abstract class BlackBox extends Module {
   // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
   // Bypass standard clock, reset, io port declaration by flattening io
   // TODO(twigg): ? Really, overrides are bad, should extend BaseModule....
-  override private[Chisel] def ports = io.elements.toSeq
+  override private[chisel] def ports = io.elements.toSeq
 
   // Do not do reflective naming of internal signals, just name io
-  override private[Chisel] def setRefs(): this.type = {
+  override private[chisel] def setRefs(): this.type = {
     for ((name, port) <- ports) {
       port.setRef(ModuleIO(this, _namespace.name(name)))
     }
@@ -40,7 +40,7 @@ abstract class BlackBox extends Module {
 
   // Don't setup clock, reset
   // Cann't invalide io in one bunch, must invalidate each part separately
-  override private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
+  override private[chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
     case Some(p) => {
       // Just init instance inputs
       for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref))
diff --git a/chiselFrontend/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/chisel/Data.scala
index d16843f7..c08adf9d 100644
--- a/chiselFrontend/src/main/scala/Chisel/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel/Data.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.language.experimental.macros
 
@@ -38,9 +38,9 @@ abstract class Data(dirArg: Direction) extends HasId {
   // Sucks this is mutable state, but cloneType doesn't take a Direction arg
   private var isFlipVar = dirArg == INPUT
   private var dirVar = dirArg
-  private[Chisel] def isFlip = isFlipVar
+  private[chisel] def isFlip = isFlipVar
 
-  private[Chisel] def overrideDirection(newDir: Direction => Direction,
+  private[chisel] def overrideDirection(newDir: Direction => Direction,
                                         newFlip: Boolean => Boolean): this.type = {
     this.isFlipVar = newFlip(this.isFlipVar)
     for (field <- this.flatten)
@@ -51,16 +51,16 @@ abstract class Data(dirArg: Direction) extends HasId {
   def asOutput: this.type = cloneType.overrideDirection(_ => OUTPUT, _ => false)
   def flip(): this.type = cloneType.overrideDirection(_.flip, !_)
 
-  private[Chisel] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[chisel] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[Chisel] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[chisel] def connect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(Connect(sourceInfo, this.lref, that.ref))
-  private[Chisel] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
+  private[chisel] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))
-  private[Chisel] def lref: Node = Node(this)
-  private[Chisel] def ref: Arg = if (isLit) litArg.get else lref
-  private[Chisel] def cloneTypeWidth(width: Width): this.type
-  private[Chisel] def toType: String
+  private[chisel] def lref: Node = Node(this)
+  private[chisel] def ref: Arg = if (isLit) litArg.get else lref
+  private[chisel] def cloneTypeWidth(width: Width): this.type
+  private[chisel] def toType: String
 
   def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = this badConnect that
 
@@ -83,7 +83,7 @@ abstract class Data(dirArg: Direction) extends HasId {
   // currently don't exist (while this information may be available during
   // FIRRTL emission, it would break directionality querying from Chisel, which
   // does get used).
-  private[Chisel] def flatten: IndexedSeq[Bits]
+  private[chisel] def flatten: IndexedSeq[Bits]
 
   /** Creates an new instance of this type, unpacking the input Bits into
     * structured data.
@@ -150,9 +150,9 @@ object Clock {
 // TODO: Document this.
 sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) {
   def cloneType: this.type = Clock(dirArg).asInstanceOf[this.type]
-  private[Chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq()
-  private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType
-  private[Chisel] def toType = "Clock"
+  private[chisel] override def flatten: IndexedSeq[Bits] = IndexedSeq()
+  private[chisel] def cloneTypeWidth(width: Width): this.type = cloneType
+  private[chisel] def toType = "Clock"
 
   override def := (that: Data)(implicit sourceInfo: SourceInfo): Unit = that match {
     case _: Clock => this connect that
diff --git a/chiselFrontend/src/main/scala/Chisel/Mem.scala b/chiselFrontend/src/main/scala/chisel/Mem.scala
index e34d5499..5fd8b81e 100644
--- a/chiselFrontend/src/main/scala/Chisel/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel/Mem.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.language.experimental.macros
 
diff --git a/chiselFrontend/src/main/scala/Chisel/Module.scala b/chiselFrontend/src/main/scala/chisel/Module.scala
index e2101538..f7f8c0b5 100644
--- a/chiselFrontend/src/main/scala/Chisel/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel/Module.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.collection.mutable.{ArrayBuffer, HashSet}
 import scala.language.experimental.macros
@@ -52,9 +52,9 @@ extends HasId {
   def this(_reset: Bool)  = this(None, Option(_reset))
   def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
 
-  private[Chisel] val _namespace = Builder.globalNamespace.child
-  private[Chisel] val _commands = ArrayBuffer[Command]()
-  private[Chisel] val _ids = ArrayBuffer[HasId]()
+  private[chisel] val _namespace = Builder.globalNamespace.child
+  private[chisel] val _commands = ArrayBuffer[Command]()
+  private[chisel] val _ids = ArrayBuffer[HasId]()
   dynamicContext.currentModule = Some(this)
 
   /** Name of the instance. */
@@ -67,18 +67,18 @@ extends HasId {
   val clock = Clock(INPUT)
   val reset = Bool(INPUT)
 
-  private[Chisel] def addId(d: HasId) { _ids += d }
+  private[chisel] def addId(d: HasId) { _ids += d }
 
-  private[Chisel] def ports: Seq[(String,Data)] = Vector(
+  private[chisel] def ports: Seq[(String,Data)] = Vector(
     ("clk", clock), ("reset", reset), ("io", io)
   )
 
-  private[Chisel] def computePorts = for((name, port) <- ports) yield {
+  private[chisel] def computePorts = for((name, port) <- ports) yield {
     val bundleDir = if (port.isFlip) INPUT else OUTPUT
     Port(port, if (port.dir == NO_DIR) bundleDir else port.dir)
   }
 
-  private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
+  private[chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
     _parent match {
       case Some(p) => {
         pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs
@@ -90,7 +90,7 @@ extends HasId {
     }
   }
 
-  private[Chisel] def setRefs(): this.type = {
+  private[chisel] def setRefs(): this.type = {
     for ((name, port) <- ports) {
       port.setRef(ModuleIO(this, _namespace.name(name)))
     }
diff --git a/chiselFrontend/src/main/scala/Chisel/Printf.scala b/chiselFrontend/src/main/scala/chisel/Printf.scala
index f068f637..27b72815 100644
--- a/chiselFrontend/src/main/scala/Chisel/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel/Printf.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.language.experimental.macros
 
@@ -29,7 +29,7 @@ object printf { // scalastyle:ignore object.name
     }
   }
 
-  private[Chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
+  private[chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
     val clock = Builder.dynamicContext.currentModule.get.clock
     pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
   }
diff --git a/chiselFrontend/src/main/scala/Chisel/Reg.scala b/chiselFrontend/src/main/scala/chisel/Reg.scala
index c8faa5c9..0ed320d7 100644
--- a/chiselFrontend/src/main/scala/Chisel/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel/Reg.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import internal._
 import internal.Builder.pushCommand
@@ -8,7 +8,7 @@ import internal.firrtl._
 import internal.sourceinfo.{SourceInfo, UnlocatableSourceInfo}
 
 object Reg {
-  private[Chisel] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
+  private[chisel] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
     if (t ne null) {
       t.cloneType
     } else if (next ne null) {
diff --git a/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel/SeqUtils.scala
index 9a15fd5f..da75edae 100644
--- a/chiselFrontend/src/main/scala/Chisel/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel/SeqUtils.scala
@@ -1,12 +1,12 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.language.experimental.macros
 
 import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
-private[Chisel] object SeqUtils {
+private[chisel] object SeqUtils {
   /** Equivalent to Cat(r(n-1), ..., r(0)) */
   def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg
 
diff --git a/chiselFrontend/src/main/scala/Chisel/When.scala b/chiselFrontend/src/main/scala/chisel/When.scala
index 90b3d1a5..37c59f24 100644
--- a/chiselFrontend/src/main/scala/Chisel/When.scala
+++ b/chiselFrontend/src/main/scala/chisel/When.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.language.experimental.macros
 
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel/internal/Builder.scala
index d0e28b7c..bacde365 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel/internal/Builder.scala
@@ -1,14 +1,14 @@
 // See LICENSE for license details.
 
-package Chisel.internal
+package chisel.internal
 
 import scala.util.DynamicVariable
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 
-import Chisel._
-import Chisel.internal.firrtl._
+import chisel._
+import firrtl._
 
-private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
+private[chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
   private var i = 0L
   private val names = collection.mutable.HashSet[String]()
 
@@ -32,7 +32,7 @@ private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]
   def child: Namespace = child(Set())
 }
 
-private[Chisel] class IdGen {
+private[chisel] class IdGen {
   private var counter = -1L
   def next: Long = {
     counter += 1
@@ -40,12 +40,12 @@ private[Chisel] class IdGen {
   }
 }
 
-private[Chisel] trait HasId {
-  private[Chisel] def _onModuleClose {} // scalastyle:ignore method.name
-  private[Chisel] val _parent = Builder.dynamicContext.currentModule
+private[chisel] trait HasId {
+  private[chisel] def _onModuleClose {} // scalastyle:ignore method.name
+  private[chisel] val _parent = Builder.dynamicContext.currentModule
   _parent.foreach(_.addId(this))
 
-  private[Chisel] val _id = Builder.idGen.next
+  private[chisel] val _id = Builder.idGen.next
   override def hashCode: Int = _id.toInt
   override def equals(that: Any): Boolean = that match {
     case x: HasId => _id == x._id
@@ -62,12 +62,12 @@ private[Chisel] trait HasId {
     for(hook <- postname_hooks) { hook(name) }
     this
   }
-  private[Chisel] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
+  private[chisel] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
 
   // Uses a namespace to convert suggestion into a true name
   // Will not do any naming if the reference already assigned.
   // (e.g. tried to suggest a name to part of a Bundle)
-  private[Chisel] def forceName(default: =>String, namespace: Namespace): Unit =
+  private[chisel] def forceName(default: =>String, namespace: Namespace): Unit =
     if(_ref.isEmpty) {
       val candidate_name = suggested_name.getOrElse(default)
       val available_name = namespace.name(candidate_name)
@@ -75,14 +75,14 @@ private[Chisel] trait HasId {
     }
 
   private var _ref: Option[Arg] = None
-  private[Chisel] def setRef(imm: Arg): Unit = _ref = Some(imm)
-  private[Chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
-  private[Chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
-  private[Chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
-  private[Chisel] def getRef: Arg = _ref.get
+  private[chisel] def setRef(imm: Arg): Unit = _ref = Some(imm)
+  private[chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
+  private[chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
+  private[chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
+  private[chisel] def getRef: Arg = _ref.get
 }
 
-private[Chisel] class DynamicContext {
+private[chisel] class DynamicContext {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
   val components = ArrayBuffer[Component]()
@@ -90,7 +90,7 @@ private[Chisel] class DynamicContext {
   val errors = new ErrorLog
 }
 
-private[Chisel] object Builder {
+private[chisel] object Builder {
   // All global mutable state must be referenced via dynamicContextVar!!
   private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
 
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/Error.scala b/chiselFrontend/src/main/scala/chisel/internal/Error.scala
index 6c4c0880..256a6d7f 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/chisel/internal/Error.scala
@@ -1,20 +1,20 @@
 // See LICENSE for license details.
 
-package Chisel.internal
+package chisel.internal
 
 import scala.collection.mutable.ArrayBuffer
 
-import Chisel._
+import chisel._
 
 class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
 
-private[Chisel] object throwException {
+private[chisel] object throwException {
   def apply(s: String, t: Throwable = null): Nothing =
     throw new ChiselException(s, t)
 }
 
 /** Records and reports runtime errors and warnings. */
-private[Chisel] class ErrorLog {
+private[chisel] class ErrorLog {
   def hasErrors: Boolean = errors.exists(_.isFatal)
 
   /** Log an error message */
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel/internal/SourceInfo.scala
index 66bfc7a4..c20bd130 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/SourceInfo.scala
+++ b/chiselFrontend/src/main/scala/chisel/internal/SourceInfo.scala
@@ -12,7 +12,7 @@
 // writers to append source locator information at the point of a library
 // function invocation.
 
-package Chisel.internal.sourceinfo
+package chisel.internal.sourceinfo
 
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
@@ -42,7 +42,7 @@ object SourceInfoMacro {
   def generate_source_info(c: Context): c.Tree = {
     import c.universe._
     val p = c.enclosingPosition
-    q"_root_.Chisel.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
+    q"_root_.chisel.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
   }
 }
 
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala
index 62784cee..9c1ce98e 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel/internal/firrtl/IR.scala
@@ -1,9 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal._
-import Chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}
+package chisel.internal.firrtl
+
+import chisel._
+import chisel.internal._
+import chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}
 
 case class PrimOp(val name: String) {
   override def toString: String = name
@@ -53,8 +54,8 @@ case class Node(id: HasId) extends Arg {
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
-  private[Chisel] def forcedWidth = widthArg.known
-  private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+  private[chisel] def forcedWidth = widthArg.known
+  private[chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
 
   protected def minWidth: Int
   if (forcedWidth) {
diff --git a/coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel/internal/sourceinfo/SourceInfoTransform.scala
index 82ad5b9e..10b677b6 100644
--- a/coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel/internal/sourceinfo/SourceInfoTransform.scala
@@ -3,7 +3,7 @@
 // This file transform macro definitions to explicitly add implicit source info to Chisel method
 // calls.
 
-package Chisel.internal.sourceinfo
+package chisel.internal.sourceinfo
 
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
@@ -23,7 +23,7 @@ trait SourceInfoTransformMacro {
   val c: Context
   import c.universe._
   def thisObj = c.prefix.tree
-  def implicitSourceInfo = q"implicitly[_root_.Chisel.internal.sourceinfo.SourceInfo]"
+  def implicitSourceInfo = q"implicitly[_root_.chisel.internal.sourceinfo.SourceInfo]"
 }
 
 class WireTransform(val c: Context) extends SourceInfoTransformMacro {
diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/Chisel/BitPat.scala
index 96206f63..a6833ed2 100644
--- a/src/main/scala/Chisel/BitPat.scala
+++ b/src/main/scala/Chisel/BitPat.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.language.experimental.macros
 
-import Chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+import chisel.internal.sourceinfo.{SourceInfo, SourceInfoTransform}
 
 object BitPat {
   /** Parses a bit pattern string into (bits, mask, width).
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/chisel/Driver.scala
index 02204684..ba2b1389 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/chisel/Driver.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import scala.sys.process._
 import java.io._
diff --git a/src/main/scala/Chisel/FileSystemUtilities.scala b/src/main/scala/chisel/FileSystemUtilities.scala
index 575ae138..f100eaf6 100644
--- a/src/main/scala/Chisel/FileSystemUtilities.scala
+++ b/src/main/scala/chisel/FileSystemUtilities.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 @deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0")
 trait FileSystemUtilities {
diff --git a/src/main/scala/Chisel/ImplicitConversions.scala b/src/main/scala/chisel/ImplicitConversions.scala
index 6a230022..f786d4f1 100644
--- a/src/main/scala/Chisel/ImplicitConversions.scala
+++ b/src/main/scala/chisel/ImplicitConversions.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 object ImplicitConversions {
   implicit def intToUInt(x: Int): UInt = UInt(x)
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/chisel/Main.scala
index a72debc3..79e5c9ca 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/chisel/Main.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 import java.io.File
 
diff --git a/src/main/scala/chisel/compatibility.scala b/src/main/scala/chisel/compatibility.scala
new file mode 100644
index 00000000..80936a42
--- /dev/null
+++ b/src/main/scala/chisel/compatibility.scala
@@ -0,0 +1,139 @@
+// See LICENSE for license details.
+
+// Allows legacy users to continue using Chisel (capital C) package name while
+// moving to the more standard package naming convention chisel (lowercase c).
+
+package object Chisel {
+  type Direction = chisel.Direction
+  val INPUT = chisel.INPUT
+  val OUTPUT = chisel.OUTPUT
+  val NO_DIR = chisel.NO_DIR
+  val debug = chisel.debug
+  type Flipped = chisel.Flipped
+  type Data = chisel.Data
+  val Wire = chisel.Wire
+  val Clock = chisel.Clock
+  type Clock = chisel.Clock
+
+  type Aggregate = chisel.Aggregate
+  val Vec = chisel.Vec
+  type Vec[T <: Data] = chisel.Vec[T]
+  type VecLike[T <: Data] = chisel.VecLike[T]
+  type Bundle = chisel.Bundle
+
+  val assert = chisel.assert
+
+  val BitPat = chisel.BitPat
+  type BitPat = chisel.BitPat
+
+  type Bits = chisel.Bits
+  val Bits = chisel.Bits
+  type Num[T <: Data] = chisel.Num[T]
+  type UInt = chisel.UInt
+  val UInt = chisel.UInt
+  type SInt = chisel.SInt
+  val SInt = chisel.SInt
+  type Bool = chisel.Bool
+  val Bool = chisel.Bool
+  val Mux = chisel.Mux
+
+  type BlackBox = chisel.BlackBox
+
+  val Mem = chisel.Mem
+  type MemBase[T <: Data] = chisel.MemBase[T]
+  type Mem[T <: Data] = chisel.Mem[T]
+  val SeqMem = chisel.SeqMem
+  type SeqMem[T <: Data] = chisel.SeqMem[T]
+
+  val Module = chisel.Module
+  type Module = chisel.Module
+
+  val printf = chisel.printf
+
+  val Reg = chisel.Reg
+
+  val when = chisel.when
+  type WhenContext = chisel.WhenContext
+
+
+  type BackendCompilationUtilities = chisel.BackendCompilationUtilities
+  val Driver = chisel.Driver
+  type FileSystemUtilities = chisel.FileSystemUtilities
+  val ImplicitConversions = chisel.ImplicitConversions
+  val chiselMain = chisel.chiselMain
+  val throwException = chisel.throwException
+
+
+  val log2Up = chisel.log2Up
+  val log2Ceil = chisel.log2Ceil
+  val log2Down = chisel.log2Down
+  val log2Floor = chisel.log2Floor
+  val isPow2 = chisel.isPow2
+
+  type ArbiterIO[T <: Data] = chisel.ArbiterIO[T]
+  type LockingArbiterLike[T <: Data] = chisel.LockingArbiterLike[T]
+  type LockingRRArbiter[T <: Data] = chisel.LockingRRArbiter[T]
+  type LockingArbiter[T <: Data] = chisel.LockingArbiter[T]
+  type RRArbiter[T <: Data] = chisel.RRArbiter[T]
+  type Arbiter[T <: Data] = chisel.Arbiter[T]
+
+  val FillInterleaved = chisel.FillInterleaved
+  val PopCount = chisel.PopCount
+  val Fill = chisel.Fill
+  val Reverse = chisel.Reverse
+
+  val Cat = chisel.Cat
+
+  val Log2 = chisel.Log2
+
+  val unless = chisel.unless
+  type SwitchContext[T <: Bits] = chisel.SwitchContext[T]
+  val is = chisel.is
+  val switch = chisel.switch
+
+  type Counter = chisel.Counter
+  val Counter = chisel.Counter
+
+  type DecoupledIO[+T <: Data] = chisel.DecoupledIO[T]
+  val Decoupled = chisel.Decoupled
+  type EnqIO[T <: Data] = chisel.EnqIO[T]
+  type DeqIO[T <: Data] = chisel.DeqIO[T]
+  type DecoupledIOC[+T <: Data] = chisel.DecoupledIOC[T]
+  type QueueIO[T <: Data] = chisel.QueueIO[T]
+  type Queue[T <: Data] = chisel.Queue[T]
+  val Queue = chisel.Queue
+
+  val Enum = chisel.Enum
+
+  val LFSR16 = chisel.LFSR16
+
+  val ListLookup = chisel.ListLookup
+  val Lookup = chisel.Lookup
+
+  val Mux1H = chisel.Mux1H
+  val PriorityMux = chisel.PriorityMux
+  val MuxLookup = chisel.MuxLookup
+  val MuxCase = chisel.MuxCase
+
+  val OHToUInt = chisel.OHToUInt
+  val PriorityEncoder = chisel.PriorityEncoder
+  val UIntToOH = chisel.UIntToOH
+  val PriorityEncoderOH = chisel.PriorityEncoderOH
+
+  val RegNext = chisel.RegNext
+  val RegInit = chisel.RegInit
+  val RegEnable = chisel.RegEnable
+  val ShiftRegister = chisel.ShiftRegister
+
+  type ValidIO[+T <: Data] = chisel.ValidIO[T]
+  val Valid = chisel.Valid
+  val Pipe = chisel.Pipe
+  type Pipe[T <: Data] = chisel.Pipe[T]
+}
+
+package Chisel {
+  package object testers {
+    type BasicTester = chisel.testers.BasicTester
+    val TesterDriver = chisel.testers.TesterDriver
+  }
+}
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/chisel/internal/firrtl/Emitter.scala
index 7ca3268a..e48eb226 100644
--- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel/internal/firrtl/Emitter.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
+package chisel.internal.firrtl
+import chisel._
+import chisel.internal.sourceinfo.{NoSourceInfo, SourceLine}
 
-private[Chisel] object Emitter {
+private[chisel] object Emitter {
   def emit(circuit: Circuit): String = new Emitter(circuit).toString
 }
 
diff --git a/src/main/scala/Chisel/package.scala b/src/main/scala/chisel/package.scala
index f05e8b5d..1abbc74f 100644
--- a/src/main/scala/Chisel/package.scala
+++ b/src/main/scala/chisel/package.scala
@@ -1,9 +1,9 @@
-package object Chisel {
+package object chisel {
   import scala.language.experimental.macros
-  
+
   import internal.firrtl.Width
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
-  
+
   implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
     def U: UInt = UInt(x, Width())
     def S: SInt = SInt(x, Width())
@@ -18,12 +18,12 @@ package object Chisel {
   implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
     def B: Bool = Bool(x)
   }
-  
+
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     final def =/= (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-  
+
     def do_=== (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that === x
     def do_!= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that != x
     def do_=/= (that: BitPat)(implicit sourceInfo: SourceInfo): Bool = that =/= x
diff --git a/src/main/scala/Chisel/testers/BasicTester.scala b/src/main/scala/chisel/testers/BasicTester.scala
index b8c1494a..36ff7c52 100644
--- a/src/main/scala/Chisel/testers/BasicTester.scala
+++ b/src/main/scala/chisel/testers/BasicTester.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 
-package Chisel.testers
-import Chisel._
+package chisel.testers
+import chisel._
 
 import scala.language.experimental.macros
 
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/chisel/testers/TesterDriver.scala
index a56bb8b7..5c0275e0 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/chisel/testers/TesterDriver.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 
-package Chisel.testers
-import Chisel._
+package chisel.testers
+
+import chisel._
 import scala.io.Source
 import scala.sys.process._
 import java.io._
diff --git a/src/main/scala/Chisel/throwException.scala b/src/main/scala/chisel/throwException.scala
index 702884aa..fdd62c7e 100644
--- a/src/main/scala/Chisel/throwException.scala
+++ b/src/main/scala/chisel/throwException.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 @deprecated("throwException doesn't exist in Chisel3", "3.0.0")
 @throws(classOf[Exception])
diff --git a/src/main/scala/Chisel/util/Arbiter.scala b/src/main/scala/chisel/util/Arbiter.scala
index 16ae9be5..afe48963 100644
--- a/src/main/scala/Chisel/util/Arbiter.scala
+++ b/src/main/scala/chisel/util/Arbiter.scala
@@ -3,7 +3,7 @@
 /** Arbiters in all shapes and sizes.
   */
 
-package Chisel
+package chisel
 
 /** An I/O bundle for the Arbiter */
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
diff --git a/src/main/scala/Chisel/util/Bitwise.scala b/src/main/scala/chisel/util/Bitwise.scala
index 239a295e..27064059 100644
--- a/src/main/scala/Chisel/util/Bitwise.scala
+++ b/src/main/scala/chisel/util/Bitwise.scala
@@ -3,7 +3,7 @@
 /** Miscellaneous circuit generators operating on bits.
   */
 
-package Chisel
+package chisel
 
 object FillInterleaved
 {
diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/chisel/util/Cat.scala
index dd706e62..a35619df 100644
--- a/src/main/scala/Chisel/util/Cat.scala
+++ b/src/main/scala/chisel/util/Cat.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 object Cat {
   /** Combine data elements together
diff --git a/src/main/scala/Chisel/util/CircuitMath.scala b/src/main/scala/chisel/util/CircuitMath.scala
index 06cab903..001be802 100644
--- a/src/main/scala/Chisel/util/CircuitMath.scala
+++ b/src/main/scala/chisel/util/CircuitMath.scala
@@ -3,7 +3,7 @@
 /** Circuit-land math operations.
   */
 
-package Chisel
+package chisel
 
 /** Compute Log2 with truncation of a UInt in hardware using a Mux Tree
   * An alternative interpretation is it computes the minimum number of bits needed to represent x
diff --git a/src/main/scala/Chisel/util/Conditional.scala b/src/main/scala/chisel/util/Conditional.scala
index 9cab25ef..94f00080 100644
--- a/src/main/scala/Chisel/util/Conditional.scala
+++ b/src/main/scala/chisel/util/Conditional.scala
@@ -3,7 +3,7 @@
 /** Conditional blocks.
   */
 
-package Chisel
+package chisel
 
 import scala.language.reflectiveCalls
 import scala.language.experimental.macros
@@ -59,7 +59,9 @@ object switch {  // scalastyle:ignore object.name
   def impl(c: Context)(cond: c.Tree)(x: c.Tree): c.Tree = { import c.universe._
     val sc = c.universe.internal.reificationSupport.freshTermName("sc")
     def extractIsStatement(tree: Tree): List[c.universe.Tree] = tree match {
-      case q"Chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      // TODO: remove when Chisel compatibility package is removed
+      case q"Chisel.`package`.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
+      case q"chisel.is.apply( ..$params )( ..$body )" => List(q"$sc.is( ..$params )( ..$body )")
       case b => throw new Exception(s"Cannot include blocks that do not begin with is() in switch.")
     }
     val q"..$body" = x
diff --git a/src/main/scala/Chisel/util/Counter.scala b/src/main/scala/chisel/util/Counter.scala
index 872e830a..dde1e347 100644
--- a/src/main/scala/Chisel/util/Counter.scala
+++ b/src/main/scala/chisel/util/Counter.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 /** A counter module
   * @param n number of counts before the counter resets (or one more than the
diff --git a/src/main/scala/Chisel/util/Decoupled.scala b/src/main/scala/chisel/util/Decoupled.scala
index 8e045855..955b0870 100644
--- a/src/main/scala/Chisel/util/Decoupled.scala
+++ b/src/main/scala/chisel/util/Decoupled.scala
@@ -3,7 +3,7 @@
 /** Wrappers for ready-valid (Decoupled) interfaces and associated circuit generators using them.
   */
 
-package Chisel
+package chisel
 
 /** An I/O Bundle with simple handshaking using valid and ready signals for data 'bits'*/
 class DecoupledIO[+T <: Data](gen: T) extends Bundle
@@ -108,7 +108,7 @@ class Queue[T <: Data](gen: T, val entries: Int,
 extends Module(override_reset=override_reset) {
   def this(gen: T, entries: Int, pipe: Boolean, flow: Boolean, _reset: Bool) =
     this(gen, entries, pipe, flow, Some(_reset))
-  
+
   val io = new QueueIO(gen, entries)
 
   val ram = Mem(entries, gen)
diff --git a/src/main/scala/Chisel/util/Enum.scala b/src/main/scala/chisel/util/Enum.scala
index 20057197..2757a06c 100644
--- a/src/main/scala/Chisel/util/Enum.scala
+++ b/src/main/scala/chisel/util/Enum.scala
@@ -3,7 +3,7 @@
 /** Enum generators, allowing circuit constants to have more meaningful names.
   */
 
-package Chisel
+package chisel
 
 object Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
diff --git a/src/main/scala/Chisel/util/LFSR.scala b/src/main/scala/chisel/util/LFSR.scala
index 839b1d1f..1befb8ca 100644
--- a/src/main/scala/Chisel/util/LFSR.scala
+++ b/src/main/scala/chisel/util/LFSR.scala
@@ -3,7 +3,7 @@
 /** LFSRs in all shapes and sizes.
   */
 
-package Chisel
+package chisel
 
 // scalastyle:off magic.number
 /** linear feedback shift register
diff --git a/src/main/scala/Chisel/util/Lookup.scala b/src/main/scala/chisel/util/Lookup.scala
index 54922fc4..1fdfd6ae 100644
--- a/src/main/scala/Chisel/util/Lookup.scala
+++ b/src/main/scala/chisel/util/Lookup.scala
@@ -1,6 +1,6 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel
 
 object ListLookup {
   def apply[T <: Data](addr: UInt, default: List[T], mapping: Array[(BitPat, List[T])]): List[T] = {
diff --git a/src/main/scala/Chisel/util/Math.scala b/src/main/scala/chisel/util/Math.scala
index 5f8212d8..1bf667ce 100644
--- a/src/main/scala/Chisel/util/Math.scala
+++ b/src/main/scala/chisel/util/Math.scala
@@ -3,7 +3,7 @@
 /** Scala-land math helper functions, like logs.
   */
 
-package Chisel
+package chisel
 
 /** Compute the log2 rounded up with min value of 1 */
 object log2Up {
diff --git a/src/main/scala/Chisel/util/Mux.scala b/src/main/scala/chisel/util/Mux.scala
index 9d92321a..97467240 100644
--- a/src/main/scala/Chisel/util/Mux.scala
+++ b/src/main/scala/chisel/util/Mux.scala
@@ -3,7 +3,7 @@
 /** Mux circuit generators.
   */
 
-package Chisel
+package chisel
 
 /** Builds a Mux tree out of the input signal vector using a one hot encoded
   select signal. Returns the output of the Mux tree.
diff --git a/src/main/scala/Chisel/util/OneHot.scala b/src/main/scala/chisel/util/OneHot.scala
index 73f27403..5d1de1a7 100644
--- a/src/main/scala/Chisel/util/OneHot.scala
+++ b/src/main/scala/chisel/util/OneHot.scala
@@ -3,7 +3,7 @@
 /** Circuit generators for working with one-hot representations.
   */
 
-package Chisel
+package chisel
 
 /** Converts from One Hot Encoding to a UInt indicating which bit is active
   * This is the inverse of [[Chisel.UIntToOH UIntToOH]]*/
diff --git a/src/main/scala/Chisel/util/Reg.scala b/src/main/scala/chisel/util/Reg.scala
index 6584a4bf..1808af76 100644
--- a/src/main/scala/Chisel/util/Reg.scala
+++ b/src/main/scala/chisel/util/Reg.scala
@@ -3,7 +3,7 @@
 /** Variations and helpers for registers.
   */
 
-package Chisel
+package chisel
 
 object RegNext {
 
diff --git a/src/main/scala/Chisel/util/TransitName.scala b/src/main/scala/chisel/util/TransitName.scala
index ec5a11cc..141b10bc 100644
--- a/src/main/scala/Chisel/util/TransitName.scala
+++ b/src/main/scala/chisel/util/TransitName.scala
@@ -1,4 +1,4 @@
-package Chisel
+package chisel
 
 import internal.HasId
 
diff --git a/src/main/scala/Chisel/util/Valid.scala b/src/main/scala/chisel/util/Valid.scala
index 9e2202bb..cffed0a7 100644
--- a/src/main/scala/Chisel/util/Valid.scala
+++ b/src/main/scala/chisel/util/Valid.scala
@@ -3,7 +3,7 @@
 /** Wrappers for valid interfaces and associated circuit generators using them.
   */
 
-package Chisel
+package chisel
 
 /** An I/O Bundle containing data and a signal determining if it is valid */
 class ValidIO[+T <: Data](gen2: T) extends Bundle