| Age | Commit message (Expand) | Author |
|---|
| 2016-09-21 | Expose FIRRTL asClock construct | Andrew Waterman |
| 2016-09-21 | Make implicit clock name consistent (#288) | Andrew Waterman |
| 2016-09-15 | Decoupled: cast DecoupledIO to IrrevocableIO as an input (#280) | Wesley W. Terpstra |
| 2016-09-13 | Bugfix: actually pass flow parameter from Queue factory to Queue module const... | Henry Cook |
| 2016-09-08 | Add IrrevocableIO alternative to DecoupledIO (#274) | Henry Cook |
| 2016-09-07 | Fix bug in Printable FullName of submodule port | jackkoenig |
| 2016-09-07 | Add Printable (#270) | Jack Koenig |
| 2016-08-25 | fix a bug in setModName | Donggyu Kim |
| 2016-08-24 | Per Chisel meeting. | chick |
| 2016-08-21 | AnnotatingExample: | chick |
| 2016-08-21 | Add AnnotationSpec file which provides an example of a way to implement gener... | chick |
| 2016-08-21 | Add annotating example to test new signal name api | chick |
| 2016-08-21 | provides signal name methods for firrtl annotation and chisel testers | Donggyu Kim |
| 2016-08-15 | Make "def width" a private API; expose isWidthKnown instead (#257) | Andrew Waterman |
| 2016-08-09 | Support Module name overrides with "override def desiredName" | Andrew Waterman |
| 2016-08-09 | counter(inc,n) example should reflect actual use (#252) | Colin Schmidt |
| 2016-07-31 | Remove deprecated FileSystemUtilities | Andrew Waterman |
| 2016-07-31 | Fix two deprecation warnings | Andrew Waterman |
| 2016-07-20 | Generate better names for nodes (#190) | Jack Koenig |
| 2016-07-11 | bitpat should keep the width of uint (#232) | Donggyu |
| 2016-07-07 | Don't check GCD result before sending it a request | Andrew Waterman |
| 2016-07-07 | Improve QoR for Log2 | Andrew Waterman |
| 2016-07-07 | Improve Fill code generation | Andrew Waterman |
| 2016-07-07 | Correct erroneous Log2 documentation | Andrew Waterman |
| 2016-07-07 | Avoid needlessly creating Vecs | Andrew Waterman |
| 2016-06-28 | Merge branch 'master' into renamechisel3 | Jim Lawson |
| 2016-06-27 | Guard firrtl stop, fixing pipelined reset | Andrew Waterman |
| 2016-06-24 | Merge branch 'master' into renamechisel3 | Jim Lawson |
| 2016-06-23 | Expose FIRRTL stop construct | Andrew Waterman |
| 2016-06-22 | Merge branch 'master' into renamechisel3 | Jim Lawson |
| 2016-06-20 | make sure MuxCase and MuxLookup can take all subclasses of Data (#222) | Howard Mao |
| 2016-06-20 | Rename "package", "import", and explicit references to "chisel3". | Jim Lawson |
| 2016-06-20 | Rename chisel3 package. | Jim Lawson |
| 2016-06-08 | Move deprecated debug into compatibility | ducky |
| 2016-06-08 | Package split chisel core | ducky |
| 2016-06-08 | Move chisel/... to chisel/core/..., make chisel/compatibility package/folder,... | ducky |
| 2016-06-08 | Move utils into utils | ducky |
| 2016-06-08 | Add implicit xToLiteral, add Element, use internal package object | ducky |
| 2016-06-08 | Rename Chisel -> chisel in tests | ducky |
| 2016-06-08 | Rename packages to lowercase chisel, add compatibility layer | ducky |
| 2016-06-01 | Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204) | Wesley W. Terpstra |
| 2016-05-31 | Remove unsafe implicit conversions from BitPat | ducky |
| 2016-05-31 | Move BitPat out of core/frontend, add implicit conversion | Ducky |
| 2016-05-26 | Fix type constraint on PriorityMux | Andrew Waterman |
| 2016-05-20 | Merge pull request #186 from ucb-bar/sloc_impl | Richard Lin |
| 2016-05-20 | Implementation of source locators | ducky |
| 2016-05-20 | Update BackendCompilationUtilities.verilogToCpp to specify top-module | jackkoenig |
| 2016-05-12 | remove Tester.scala because chiselMain is now implemented in the chisel-teste... | Danny |
| 2016-05-11 | RegNext and RegInit should match Reg(next=) and Reg(init=) | Andrew Waterman |
| 2016-05-10 | Move emit out of IR | ducky |
