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path: root/src/test/scala/chiselTests/Vec.scala
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2022-11-10 Warn on S-interpolator usage for assert, assume and printf (backport #2751) ↵Aditya Naik
(#2757) * Add internal methods to maintain binary compatibility Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-09-27Use Treadle (on pull requests only) to speed up CI (backport #2341) (#2748)mergify[bot]
* Support using Treadle for 'sbt test' Treadle will be used as the "defaultBackend" when the environment variable CHISEL3_CI_USE_TREADLE is set. The intent is to set this variable during CI for pre-merge CI (aka on pull requests). (cherry picked from commit 7d39b7bd2b6f38dac90fe25064744ffc0ada0fe4) * Use Treadle for CI on pull requests (cherry picked from commit 82660673e56a816e68fcc068e3e04e127f076faf) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-05-24Support Vecs of empty Bundles (#2543) (#2545)mergify[bot]
(cherry picked from commit a1e3a6b5324997864168111bee8c02a60abb0acc) Co-authored-by: Jack Koenig <koenig@sifive.com>
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2021-12-11reduceTree() now operates on Seq (#2292)Øyvind Harboe
preserves input/output information of the type being reduced. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2021-08-23Add multiple dimensions to VecInit fill and iterate (#2065)anniej-sifive
Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-08-04Added VecInit factory methods (fill,iterate) (#2059)anniej-sifive
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-06-22Use ChiselStage in TestsSchuyler Eldridge
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-08Require target is hardware for Vec.apply(a: UInt)Schuyler Eldridge
Adds a check that a Vec being indexed by a UInt is, in fact, a hardware type. This includes a test for this. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-05-20Repackagecore rebase (#1078)Jim Lawson
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. * Move Aggregate, Clock, Mem, Printf, Reg * Move almost all chisel3.core definitions to chisel3 or chisel3.experimental * Revive core package object to provide aliases for moved definitions. * Cleanup package definitions; eliminate ambiguous implicits * Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. * Put BitPat back in chisel3.util * More experimental motion - avoid multiple import definitions. * Add experimental.FixedPoint alias * Add EnumType definition to core package. Update deprecated messages to refer to correct object * Move FixedPoint into the experimental package (but keep it in Bits.scala). * Add missing implicits to core/package - compatibility * Cleanup: update ScalaDoc references; remove unused imports * Add Reset alias to core/package * Use common 3.2 version in deprecation warning * Move Binding from core to internal. * Optimize imports. * Repair IntelliJ's overly cleanliness. * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. * Change == to reference equality (eq) in Data print (#1044) * Remove @chiselName from MixedVec (#1045) * Fix enum annotations (#936) * Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style * Add Record to type hierarchy documentation * Undeprecate isLit (#1048) * move doNotDedup to experimental (#1008) * Aggregate coverage - aggregate tests but not publishing (#1040) Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772. * Check field referential equality in autoclonetype (#1047) * Allow naming annotation to work outside builder context (#1051) * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Make core.DontCare private to chisel3 (#1054) Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object. * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Detect bundle aliasing (#1050) * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Optimize imports. * Move Analog to experimental. * More repackage cleanup - reduce differences with master. * Cleanup chisel3 references. * More chisel3 reference cleanup. * Merge cleanup. * Remove unused import * Bump core deprecation to 3.3 * Move DontCare back into Data.scala inside package internal * Re-indent experimental/internal package code * Move code back to original files - facilitate comparison with other branches * Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. * More master diff minimization. * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Move Analog to experimental. More repackage cleanup - reduce differences with master. Cleanup chisel3 references. More chisel3 reference cleanup. * Fix wrong directionality for Vec(Flipped()) Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063 * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Put BitPat back in chisel3.util More experimental motion - avoid multiple import definitions. Add experimental.FixedPoint alias Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Add Reset alias to core/package Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Repair IntelliJ's overly cleanliness. Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Merge cleanup. Remove unused import Bump core deprecation to 3.3 Move DontCare back into Data.scala inside package internal Re-indent experimental/internal package code Move code back to original files - facilitate comparison with other branches Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. More master diff minimization. Fix minor discrepancies with repackagecore-testbed * Remove redundant imports As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._` * Move the BaseModule object into the internal package.
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-21Support DontCare in Mux and cloneSupertype (#995)Richard Lin
2018-01-19Fix deprecations in testsducky
2017-12-20Add compileOptions to Module.apply, use for invalidating submod ports (#747)Jack Koenig
Fixes #746 Also add test for https://github.com/freechipsproject/firrtl/issues/705
2017-12-14Add error message for <> of Vec and Seq of different lengths (#739)Jack Koenig
Fixes #482
2017-10-26Invalidateapi (#645)Adam Izraelevitz
* Require explicit connection to DontCare to generate "is invalid". * Add tests for RefNotInitializedException. Currently, we fail the when ... otherwise ... * Disable ScalaTest shrinking on error in ComplexAssignSpec. * fix broken merge; still some binding issues * cleanup DontCare connection checks; add missing directions to test module IOs * Have library code inherit compileOptions from the enclosing Module (if it exists). * work around current firrtl uninitialized references with Strict compile options and explicitInvalidate * more CompileOptions cleanup; move test-specific defines to package object * minimize differences with master * set default CompileOptions.explicitInvalidate to false until we fix the FIRRTL when issue * ignore the StrictCompiler property checks (until CompileOptions.explicitInvalidate is defaulted to true) * Revert "more CompileOptions cleanup; move test-specific defines to package object" This reverts commit e4486edcba990d150e76e08a2fc6abca033556e0. * Revert "work around current firrtl uninitialized references with Strict compile options and explicitInvalidate" This reverts commit 426faa430a62c3dac2dbdf33044d3386d4243157. * remove unused code * Convert to binding-based DontCare implementation * comment cleanup to minimize differences with master * Tentatively remove possibly redundant DefInvalid on module ports. * Respond to code review change request. - backout build.sbt change - correct indentation - handle bulk of DontCare semantics in elemConnect() - have DontCare extend Element, not Data (eliminate most Object specific methods - add comments indicating reason for explicit DontCare connections * Initialize test elements without requiring a DontCare. * Respond to review change requests. - DontCare should work on left or right side in BiDirectional connections - call bind() to set DontCare binding instead of messing with internal variables - DontCares are only equivalent with DontCares - clean up processWhens() definition * Eliminate DontCare connection to inputs in MonoConnect(). * Pull aggregates apart for the purpose of DontCare connections. * Restore the explicit (conditionally executed) ports DefInvalidin ImplicitModule() * Don't add DontCare's to the module list of _ids. * Add missing DefInvalid() to LegacyModule(). * Respond to review requests: add DontCare BiConnect Vec, remove null parent hack to avoid addId(), initialize singletons early in Builder * Move DontCare out of chisel3.experimental.
2017-10-05the cloneType and chiselCloneType hot mess 🔥 (#653)Richard Lin
Addresses #419 cloneType is now marked (through comments only) as an internal API. chiselCloneType deprecated (and changed to cloneTypeFull internally, analogous to cloneTypeWidth). chiselTypeOf(data) introduced as the external API to get a chisel type from a hardware object Intended usage: cloning is an implementation detail, and chisel types and hardware objects both should act as immutable types, with operations like Input(...), Reg(...), etc returning a copy and leaving the original unchanged. Hence, the clone operations are all deprecated. Deletes what appears to be an unused Bundle companion object. Input(...), Output(...), Flipped(...) require the object to be unbound
2017-08-17More of the bindings refactor (#635)Richard Lin
Rest of the binding refactor
2017-04-15 Fix assignment from 0-entry Vec: add test (#580)Andrew Waterman
* Partially revert 8e4ddc62db448b613ae327792e72defca4d115d4 It was an incomplete fix for handling Vec(0). * Fix assignment from 0-entry Vec: add test 375e2b6a0a456c55298d82837d28986de6211ebc introduced a regression for bundles containing zero-entry Vecs. Until zero-width UInts are supported, the zero-entry Vecs need to be flattened out before doing asUInt/asTypeOf on a bundle. Undoing that commit's replacement of Data.flatten with Aggregate.getElements is the best interim fix.
2017-04-04Use input element to decide if Vec of values has direction (#570)Jack Koenig
Using the sample_element of the created wire is incorrect because Wires have no direction so the Wire constructed for a Vec of Module IO was constructed incorrectly. Fixes #569 and resolves #522.
2017-03-27Support Vec(0) fields in Bundles, just like Option[Data]; add testAndrew Waterman
This also allows asUInt/asTypeOf to work properly on those Bundles, even though zero-width wire support is lacking.
2017-03-24Fix getWidth on empty Vecs; add testAndrew Waterman
Use fold(0) instead of reduce to handle the corner case.
2017-03-13Revert "Change Vec creation to check if gen is lit (and hence needs t… (#530)Jim Lawson
* Revert "Change Vec creation to check if gen is lit (and hence needs to be declared)" This reverts commit dc86e7e1734d6abacb739b488df1de231e6b41b2. This may address #522 - using chiselCloneType (instead of cloneType) to preserve directionality. * Add missing implicits to Vec.apply() signature. * Use correct macro (CompileOptionsTransform) for indexWhere.
2017-03-08Deprecate old Reg with nulls constructor (#455)Richard Lin
2017-03-08Avoid log2Up in ShiftRegisterTesterAndrew Waterman
This is an odd one. Using log2Ceil directly results in a Verilator compile error, presumably due to a FIRRTL zero-width wire bug.
2017-02-24Test that large Vecs can have widths inferredjackkoenig
Test for ucb-bar/firrtl#407
2017-02-03Added vec IO tests for #104 (#480)Jim Lawson
* Added vec IO tests for #104 * Added Vec test case for Reg of vecs * Change Vec creation to check if gen is lit (and hence needs to be declared) Fixes #104 * Fix tests (add IO())), Vec.fill() * Fix deprecated usage. * Add Binding IO() NPE fix so tests pass. * Fix style - use space consistently. * Fix style - use space consistently.
2016-11-21Fix all deprecations from new styleducky
2016-11-21All remaining automatable regex re-stylesducky
2016-11-21Restyle a lot of test code, mainly with regexducky
2016-10-06Merge branch 'master' into tobits-deprecationJim Lawson
2016-09-29Consolidate CompileOptions and re-enable NotStrict pending macro work.Jim Lawson
2016-09-29Massive rename of CompileOptions.Jim Lawson
Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports. NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence). We should really thread the CompileOptions through the macro system so the client's implicits are used.
2016-09-01Move connection implicits from Module constructor to connection methods.Jim Lawson
Eliminate builder compileOptions.
2016-07-25Minimize differences with master.Jim Lawson
Remove .Lit(x) usage. Undo "private" scope change. Change "firing" back to "fire". Add package level NODIR definition.
2016-07-20More literal/width rangling.Jim Lawson
2016-07-20Distinguish between ?Int.Lit and ?Int.widthJim Lawson
2016-07-19Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3Jim Lawson
2016-07-18Update Chisel -> chisel3 references.Jim Lawson
2016-06-21New Module, IO, Input/Output wrapping.Jim Lawson
2016-06-06Changed deprecation warning for Data#toBits to recommend asUInt instead ↵chick
because the sole remaining use of toBits in chiselTests was to compare to Vectors declared differently but with same underlying bits. Making at toBits was problematic because it did not support === method. Changed Vec and Bundle to both support toUInt() Note: If toBits is actually needed now, one can use toInt().toBits()
2016-06-01Fix a fairly serious bug whereby Vec's could incorrectly compare as equal (#204)Wesley W. Terpstra
* chiselTests: include an example of two empty Vectors killing FIRRTL * Aggregate: fix a bug whereby Vec[T] was using equals/hashCode of Seq In Chisel, two vectors are NOT equal just if their contents are equal. For example, two empty vectors should not be considered equal. This patch makes Vec use the HasId._id for equality like other Chisel types. Without this fix, Bundle.namedElts.seen: HashSet[Data]() will eliminate one of the named vectors and emit bad IR.
2016-04-26Replace deprecated usage in tests. Issue #149Jim Lawson
2016-01-30Add BlackBox support and test, refactor execute => assertTesterPassesducky
2015-12-11Refactor tests to use stop() and assert() instead of io.error/io.doneducky
Gate assert, printf, stop by reset Fix testbenches that never worked Change simulation prints to display cycle at which test was signaled to end, not when simulator stops Better documentation for Counter
2015-11-06Fixed bug that created Vec(Reg(...)) instead of Reg(Vec(...))azidar
2015-11-04Remove Parameters library and refactor Driver.Henry Cook
In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances, this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester. The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed. Further work is needed on individual tests to use assertions instead of .io.error.
2015-10-23Whitespace scalastyle fixes for testsducky
2015-08-14VecShiftReg testHenry Cook
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