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authorducky2015-12-10 16:22:59 -0800
committerducky2016-01-30 14:45:55 -0800
commit898efea92e9e13775b39dd7fb92cac420334b9c9 (patch)
treebb7cdb52fbfe90c44de5846f5175b27d894e3b27 /src/test/scala/chiselTests/Vec.scala
parent8d8c407c0c1693160d6f0972165e376e09aa99c9 (diff)
Add BlackBox support and test, refactor execute => assertTesterPasses
Diffstat (limited to 'src/test/scala/chiselTests/Vec.scala')
-rw-r--r--src/test/scala/chiselTests/Vec.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 0c3d046e..f48c1b63 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -44,15 +44,15 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
class VecSpec extends ChiselPropSpec {
property("Vecs should be assignable") {
forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) =>
- assert(execute{ new ValueTester(w, v) })
+ assertTesterPasses{ new ValueTester(w, v) }
}
}
property("Vecs should tabulate correctly") {
- forAll(smallPosInts) { (n: Int) => assert(execute{ new TabulateTester(n) }) }
+ forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new TabulateTester(n) } }
}
property("Regs of vecs should be usable as shift registers") {
- forAll(smallPosInts) { (n: Int) => assert(execute{ new ShiftRegisterTester(n) }) }
+ forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } }
}
}