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authorRichard Lin2017-03-08 17:38:14 -0800
committerGitHub2017-03-08 17:38:14 -0800
commita290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch)
tree3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/test/scala/chiselTests/Vec.scala
parent09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff)
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/test/scala/chiselTests/Vec.scala')
-rw-r--r--src/test/scala/chiselTests/Vec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 4dcd6a47..c9320a96 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -20,7 +20,7 @@ class RegTesterMod(vecSize: Int) extends Module {
val in = Input(Vec(vecSize, UInt()))
val out = Output(Vec(vecSize, UInt()))
})
- val vecReg = Reg(init = Vec(vecSize, 0.U), next = io.in)
+ val vecReg = RegNext(io.in, Vec(vecSize, 0.U))
io.out := vecReg
}