Deprecate old Reg with nulls constructor (#455)

12 files changed, 29 insertions, 36 deletions

diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index 076786cd..92559123 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester {
 
 class PipelinedResetModule extends Module {
   val io = IO(new Bundle { })
-  val a = Reg(init = 0xbeef.U)
-  val b = Reg(init = 0xbeef.U)
+  val a = RegInit(0xbeef.U)
+  val b = RegInit(0xbeef.U)
   assert(a === b)
 }
 
@@ -36,7 +36,7 @@ class PipelinedResetModule extends Module {
 class PipelinedResetTester extends BasicTester {
   val module = Module(new PipelinedResetModule)
 
-  module.reset := Reg(next = Reg(next = Reg(next = reset)))
+  module.reset := RegNext(RegNext(RegNext(reset)))
 
   val (_, done) = Counter(!reset, 4)
   when (done) {
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 55c07772..b85d37a1 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -18,7 +18,7 @@ class CountTester(max: Int) extends BasicTester {
 }
 
 class EnableTester(seed: Int) extends BasicTester {
-  val ens = Reg(init = seed.asUInt)
+  val ens = RegInit(seed.asUInt)
   ens := ens >> 1
 
   val (cntEnVal, _) = Counter(ens(0), 32)
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 6dc4aac6..94e54760 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -10,10 +10,10 @@ class EnableShiftRegister extends Module {
     val shift = Input(Bool())
     val out   = Output(UInt(4.W))
   })
-  val r0 = Reg(init = 0.U(4.W))
-  val r1 = Reg(init = 0.U(4.W))
-  val r2 = Reg(init = 0.U(4.W))
-  val r3 = Reg(init = 0.U(4.W))
+  val r0 = RegInit(0.U(4.W))
+  val r1 = RegInit(0.U(4.W))
+  val r2 = RegInit(0.U(4.W))
+  val r3 = RegInit(0.U(4.W))
   when(io.shift) {
     r0 := io.in
     r1 := r0
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index c20d26ad..499ab591 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -26,7 +26,7 @@ class GCD extends Module {
 
 class GCDTester(a: Int, b: Int, z: Int) extends BasicTester {
   val dut = Module(new GCD)
-  val first = Reg(init=true.B)
+  val first = RegInit(true.B)
   dut.io.a := a.U
   dut.io.b := b.U
   dut.io.e := first
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index 09beddb9..7b798518 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -11,7 +11,7 @@ class LFSR16 extends Module {
     val inc = Input(Bool())
     val out = Output(UInt(16.W))
   })
-  val res = Reg(init = 1.U(16.W))
+  val res = RegInit(1.U(16.W))
   when (io.inc) {
     val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
     res := nxt_res
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 4cbedf58..d36167a4 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -13,7 +13,7 @@ class MemorySearch extends Module {
     val address = Output(UInt(3.W))
   })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
-  val index = Reg(init = 0.U(3.W))
+  val index = RegInit(0.U(3.W))
   val elts  = Vec(vals.map(_.asUInt(4.W)))
   // val elts  = Mem(UInt(32.W), 8) TODO ????
   val elt  = elts(index)
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 933ce2b9..23c984b5 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
 
 import chisel3._
 import chisel3.experimental.{withClockAndReset, withClock, withReset}
-import chisel3.util.{Counter, RegInit}
+import chisel3.util.Counter
 import chisel3.testers.BasicTester
 
 /** Multi-clock test of a Reg using a different clock via withClock */
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index ef66c30a..7de85d04 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -11,39 +11,32 @@ import chisel3.core.DataMirror
 import chisel3.testers.BasicTester
 
 class RegSpec extends ChiselFlatSpec {
-  "A Reg" should "throw an exception if not given any parameters" in {
-    a [Exception] should be thrownBy {
-      val reg = Reg()
-    }
-  }
-
-  "A Reg" should "be of the same type and width as outType, if specified" in {
+  "Reg" should "be of the same type and width as t" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(2.W), next=Wire(UInt(3.W)), init=20.U)
-      reg.getWidth should be (2)
+      val reg = Reg(UInt(2.W))
+      DataMirror.widthOf(reg) should be (2.W)
     }
     elaborate{ new RegOutTypeWidthTester }
   }
 
-  "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
+  "RegNext" should "be of unknown width" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=Wire(UInt(3.W)), init=20.U)
-      reg1.isWidthKnown should be (false)
+      val reg1 = RegNext(2.U(3.W))
       DataMirror.widthOf(reg1).known should be (false)
-      val reg2 = Reg(init=20.U)
-      reg2.isWidthKnown should be (false)
+      val reg2 = RegNext(2.U(3.W), 4.U)
       DataMirror.widthOf(reg2).known should be (false)
-      val reg3 = Reg(next=Wire(UInt(3.W)), init=5.U)
-      reg3.isWidthKnown should be (false)
+      val reg3 = RegNext(2.U(3.W), 4.U(5.W))
       DataMirror.widthOf(reg3).known should be (false)
     }
     elaborate { new RegUnknownWidthTester }
   }
 
-  "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
+  "RegInit" should "have width only if specified in the literal" in {
     class RegForcedWidthTester extends BasicTester {
-      val reg2 = Reg(init=20.U(7.W))
-      reg2.getWidth should be (7)
+      val reg1 = RegInit(20.U)
+      DataMirror.widthOf(reg1).known should be (false)
+      val reg2 = RegInit(20.U(7.W))
+      DataMirror.widthOf(reg2) should be (7.W)
     }
     elaborate{ new RegForcedWidthTester }
   }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 0d03ff65..07efb7dc 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -17,7 +17,7 @@ class Risc extends Module {
   val memSize = 256
   val file = Mem(memSize, Bits(32.W))
   val code = Mem(memSize, Bits(32.W))
-  val pc   = Reg(init=0.U(8.W))
+  val pc   = RegInit(0.U(8.W))
 
   val add_op :: imm_op :: Nil = Enum(2)
 
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index df1e68bf..3cdb68eb 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -17,8 +17,8 @@ class ChiselStack(val depth: Int) extends Module {
   })
 
   val stack_mem = Mem(depth, UInt(32.W))
-  val sp        = Reg(init = 0.U(log2Ceil(depth+1).W))
-  val out       = Reg(init = 0.U(32.W))
+  val sp        = RegInit(0.U(log2Ceil(depth+1).W))
+  val out       = RegInit(0.U(32.W))
 
   when (io.en) {
     when(io.push && (sp < depth.asUInt)) {
diff --git a/src/test/scala/chiselTests/Stop.scala b/src/test/scala/chiselTests/Stop.scala
index 1c2d390d..136fafc8 100644
--- a/src/test/scala/chiselTests/Stop.scala
+++ b/src/test/scala/chiselTests/Stop.scala
@@ -11,7 +11,7 @@ class StopTester() extends BasicTester {
 }
 
 class StopImmediatelyTester extends BasicTester {
-  val cycle = Reg(init = 0.asUInt(4.W))
+  val cycle = RegInit(0.asUInt(4.W))
   cycle := cycle + 1.U
   when (cycle === 4.U) {
     stop()
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 4dcd6a47..c9320a96 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -20,7 +20,7 @@ class RegTesterMod(vecSize: Int) extends Module {
     val in = Input(Vec(vecSize, UInt()))
     val out = Output(Vec(vecSize, UInt()))
   })
-  val vecReg = Reg(init = Vec(vecSize, 0.U), next = io.in)
+  val vecReg = RegNext(io.in, Vec(vecSize, 0.U))
   io.out := vecReg
 }