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Diffstat (limited to 'src/test/scala/chiselTests/EnableShiftRegister.scala')
| -rw-r--r-- | src/test/scala/chiselTests/EnableShiftRegister.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 6dc4aac6..94e54760 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -10,10 +10,10 @@ class EnableShiftRegister extends Module { val shift = Input(Bool()) val out = Output(UInt(4.W)) }) - val r0 = Reg(init = 0.U(4.W)) - val r1 = Reg(init = 0.U(4.W)) - val r2 = Reg(init = 0.U(4.W)) - val r3 = Reg(init = 0.U(4.W)) + val r0 = RegInit(0.U(4.W)) + val r1 = RegInit(0.U(4.W)) + val r2 = RegInit(0.U(4.W)) + val r3 = RegInit(0.U(4.W)) when(io.shift) { r0 := io.in r1 := r0 |