diff options
| author | Richard Lin | 2017-03-08 17:38:14 -0800 |
|---|---|---|
| committer | GitHub | 2017-03-08 17:38:14 -0800 |
| commit | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch) | |
| tree | 3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/test/scala/chiselTests/EnableShiftRegister.scala | |
| parent | 09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff) | |
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/test/scala/chiselTests/EnableShiftRegister.scala')
| -rw-r--r-- | src/test/scala/chiselTests/EnableShiftRegister.scala | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 6dc4aac6..94e54760 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -10,10 +10,10 @@ class EnableShiftRegister extends Module { val shift = Input(Bool()) val out = Output(UInt(4.W)) }) - val r0 = Reg(init = 0.U(4.W)) - val r1 = Reg(init = 0.U(4.W)) - val r2 = Reg(init = 0.U(4.W)) - val r3 = Reg(init = 0.U(4.W)) + val r0 = RegInit(0.U(4.W)) + val r1 = RegInit(0.U(4.W)) + val r2 = RegInit(0.U(4.W)) + val r3 = RegInit(0.U(4.W)) when(io.shift) { r0 := io.in r1 := r0 |
