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Diffstat (limited to 'src/test/scala/chiselTests/LFSR16.scala')
| -rw-r--r-- | src/test/scala/chiselTests/LFSR16.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala index 09beddb9..7b798518 100644 --- a/src/test/scala/chiselTests/LFSR16.scala +++ b/src/test/scala/chiselTests/LFSR16.scala @@ -11,7 +11,7 @@ class LFSR16 extends Module { val inc = Input(Bool()) val out = Output(UInt(16.W)) }) - val res = Reg(init = 1.U(16.W)) + val res = RegInit(1.U(16.W)) when (io.inc) { val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1)) res := nxt_res |