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-rw-r--r--src/test/scala/chiselTests/MultiClockSpec.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/scala/chiselTests/MultiClockSpec.scala b/src/test/scala/chiselTests/MultiClockSpec.scala
index 933ce2b9..23c984b5 100644
--- a/src/test/scala/chiselTests/MultiClockSpec.scala
+++ b/src/test/scala/chiselTests/MultiClockSpec.scala
@@ -4,7 +4,7 @@ package chiselTests
import chisel3._
import chisel3.experimental.{withClockAndReset, withClock, withReset}
-import chisel3.util.{Counter, RegInit}
+import chisel3.util.Counter
import chisel3.testers.BasicTester
/** Multi-clock test of a Reg using a different clock via withClock */