diff options
| author | ducky | 2015-12-11 14:25:42 -0800 |
|---|---|---|
| committer | ducky | 2015-12-11 17:16:30 -0800 |
| commit | dbd072172f6312893e1922e48ed768ae0fab9a89 (patch) | |
| tree | c3a0f10dd286ae2bba50c31b987ab39c45189898 /src/test/scala/chiselTests/Vec.scala | |
| parent | bffc67c2bbeb107d2ff9903aa35e85fbb7da73f9 (diff) | |
Refactor tests to use stop() and assert() instead of io.error/io.done
Gate assert, printf, stop by reset
Fix testbenches that never worked
Change simulation prints to display cycle at which test was signaled to end, not when simulator stops
Better documentation for Counter
Diffstat (limited to 'src/test/scala/chiselTests/Vec.scala')
| -rw-r--r-- | src/test/scala/chiselTests/Vec.scala | 30 |
1 files changed, 17 insertions, 13 deletions
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala index 6d16ec08..0c3d046e 100644 --- a/src/test/scala/chiselTests/Vec.scala +++ b/src/test/scala/chiselTests/Vec.scala @@ -8,36 +8,40 @@ import org.scalatest.prop._ import Chisel.testers.BasicTester class ValueTester(w: Int, values: List[Int]) extends BasicTester { - io.done := Bool(true) val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error? - io.error := v.zip(values).map { case(a,b) => - a != UInt(b) - }.foldLeft(UInt(0))(_##_) + for ((a,b) <- v.zip(values)) { + assert(a === UInt(b)) + } + stop() } class TabulateTester(n: Int) extends BasicTester { - io.done := Bool(true) val v = Vec(Range(0, n).map(i => UInt(i * 2))) val x = Vec(Array.tabulate(n){ i => UInt(i * 2) }) val u = Vec.tabulate(n)(i => UInt(i*2)) - when(v.toBits != x.toBits) { io.error := UInt(1) } - when(v.toBits != u.toBits) { io.error := UInt(2) } - when(x.toBits != u.toBits) { io.error := UInt(3) } + + assert(v.toBits === x.toBits) + assert(v.toBits === u.toBits) + assert(x.toBits === u.toBits) + + stop() } class ShiftRegisterTester(n: Int) extends BasicTester { val (cnt, wrap) = Counter(Bool(true), n*2) - when(wrap) { io.done := Bool(true) } - val shifter = Reg(Vec(UInt(width = log2Up(n)), n)) (shifter, shifter drop 1).zipped.foreach(_ := _) shifter(n-1) := cnt - val expected = cnt - UInt(n) - when(cnt >= UInt(n) && expected != shifter(0)) { io.done := Bool(true); io.error := expected } + when (cnt >= UInt(n)) { + val expected = cnt - UInt(n) + assert(shifter(0) === expected) + } + when (wrap) { + stop() + } } class VecSpec extends ChiselPropSpec { - property("Vecs should be assignable") { forAll(safeUIntN(8)) { case(w: Int, v: List[Int]) => assert(execute{ new ValueTester(w, v) }) |
