Add compileOptions to Module.apply, use for invalidating submod ports (#747)

Fixes #746
Also add test for https://github.com/freechipsproject/firrtl/issues/705

1 files changed, 1 insertions, 10 deletions

diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 08b9cdf5..bf25ed82 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import chisel3._
+import chisel3.experimental.RawModule
 import chisel3.core.Binding.BindingException
 import chisel3.testers.BasicTester
 import chisel3.util._
@@ -153,16 +154,6 @@ class ZeroEntryVecTester extends BasicTester {
   stop()
 }
 
-class PassthroughModuleIO extends Bundle {
-  val in = Input(UInt(32.W))
-  val out = Output(UInt(32.W))
-}
-
-class PassthroughModule extends Module {
-  val io = IO(new PassthroughModuleIO)
-  io.out := io.in
-}
-
 class PassthroughModuleTester extends Module {
   val io = IO(Flipped(new PassthroughModuleIO))
   // This drives the input of a PassthroughModule