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path: root/src/test/scala/chiselTests/PrintableSpec.scala
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2022-06-01Add formatted Printable interpolator `cf` (#2528) (#2553)mergify[bot]
This is a formatted version of the p"..." interpolator analogous to Scala's f"..." interpolator. The primary difference is that it supports formatting interpolated variables by following the variable with "%<specifier>". For example: printf(cf"myWire = $myWire%x\n") This will format the hardware value "myWire" as a hexidecimal value in the emitted Verilog. Note that literal "%" must be escaped as "%%". Scala types and format specifiers are supported and are handled in the same manner as in standard Scala f"..." interpolators. (cherry picked from commit 037f7b2ff3a46184d1b82e1b590a7572bfa6a76b) Co-authored-by: Girish Pai <girish.pai@sifive.com>
2022-01-10Apply scalafmtJack Koenig
Command: sbt scalafmtAll
2021-10-05Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)Megan Wachs
* Remove all manual cloneTypes and make it chisel runtime deprecated to add one * runtime deprecate cloneType with runtime reflection * [Backport this commit] Bundle: add check that override def cloneType still works (will be made an error later) * Plugin: make it an error to override cloneType and add a test for that * Docs: can't compile the cloneType anymore * BundleSpec: comment out failing test I cannot get to fail or ignore Co-authored-by: Jack Koenig <koenig@sifive.com>
2021-09-23make all verification statements publically available (#2089)Kevin Laeufer
2021-08-23Remove chisel3's own firrtl Emitter, use firrtl SerializerJack Koenig
This will be slightly slower as it involves converting from Chisel modules to FIRRTL modules before turning them into Strings. This cost is somewhat mitigated by doing that conversion lazily such that we never materialize the entire firrtl Circuit in memory, only 1 module at a time.
2021-07-06Make printf return BaseSim subclass so it can be named/annotated (#1992)Deborah Soung
2020-10-01Move Chisel3 to SPDX license conventions (#1604)Chick Markley
Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ```
2020-08-26Add ChiselPhase, Stop writing files in ChiselStage$ methods, Expand ↵Schuyler Eldridge
ChiselStage$ helpers (#1566) * Add ChiselPhase * Use ChiselPhase in ChiselStage, remove targets Switch from a one-off PhaseManager inside ChiselStage to actually using the newly added ChiselPhase. This removes the targets method (and API) from ChiselStage. * Stop writing to files in ChiselStage$ methods Change the ChiselStage companion object methods, elaborate and convert, to not write files. Under the hood, these are switched from using ChiselStage (which, like all phases, will write files) to using ChiselPhase. * Test that ChiselStage$ methods write no files Modify existing ChiselStage object method tests to check that no files are written. * Expand ChiselStage$ API with more helpers This adds additional methods to the ChiselStage object for going directly from a Chisel module to a string including: CHIRRTL, high FIRRTL IR, Verilog, and SystemVerilog. Differing from their ChiselStage class counterparts, these take no arguments other than the module and write no files. * Add tests of new ChiselStage$ helper methods * Use ChiselStage object in tests Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-07-21Delete outdated scalastyle configuration comments from sourceAlbert Magyar
2020-06-22Use ChiselStage in TestsSchuyler Eldridge
This migrates the tests to Chisel 3.4/FIRRTL 1.4. This primarily involves removing usages of deprecated methods including: - Remove usages of Driver - Use ChiselStage methods instead of BackendCompilationUtilities methods - Use Dependency API for custom transforms - Use extractCause to unpack StackError Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Update scalatest to 3.1.0 (#1394)Jim Lawson
Co-authored-by: Scala Steward <me@scala-steward.org>
2020-02-10Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)Jack Koenig
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-05-20Repackagecore rebase (#1078)Jim Lawson
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. * Move Aggregate, Clock, Mem, Printf, Reg * Move almost all chisel3.core definitions to chisel3 or chisel3.experimental * Revive core package object to provide aliases for moved definitions. * Cleanup package definitions; eliminate ambiguous implicits * Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. * Put BitPat back in chisel3.util * More experimental motion - avoid multiple import definitions. * Add experimental.FixedPoint alias * Add EnumType definition to core package. Update deprecated messages to refer to correct object * Move FixedPoint into the experimental package (but keep it in Bits.scala). * Add missing implicits to core/package - compatibility * Cleanup: update ScalaDoc references; remove unused imports * Add Reset alias to core/package * Use common 3.2 version in deprecation warning * Move Binding from core to internal. * Optimize imports. * Repair IntelliJ's overly cleanliness. * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. * Change == to reference equality (eq) in Data print (#1044) * Remove @chiselName from MixedVec (#1045) * Fix enum annotations (#936) * Turned off strong enum annotations because they weren't working with Vec indexes * Add new EnumVecAnnotation for vecs of enums and vecs of bundles with enum fields * Changed Clock's width parameter back to a fixed constant value of 1 * Fixed enum annotations for Vecs of Bundles which contain enum elements * Fixed usage of "when/otherwise" to use consistent style * Add Record to type hierarchy documentation * Undeprecate isLit (#1048) * move doNotDedup to experimental (#1008) * Aggregate coverage - aggregate tests but not publishing (#1040) Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml This should finally fix #772. * Check field referential equality in autoclonetype (#1047) * Allow naming annotation to work outside builder context (#1051) * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Make core.DontCare private to chisel3 (#1054) Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object. * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Detect bundle aliasing (#1050) * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Optimize imports. * Move Analog to experimental. * More repackage cleanup - reduce differences with master. * Cleanup chisel3 references. * More chisel3 reference cleanup. * Merge cleanup. * Remove unused import * Bump core deprecation to 3.3 * Move DontCare back into Data.scala inside package internal * Re-indent experimental/internal package code * Move code back to original files - facilitate comparison with other branches * Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. * More master diff minimization. * Try to eliminate JVM hang due to static initialization deadlock (#1053) * Ignore empty aggregates elements when binding aggregate direction (#946) Previously, including an empty aggregate in a Bundle would cause a MixedDirectionAggregateException because it has no elements and thus doesn't have a direction * Add SampleElementBinding for Vec sample elements * Add ActualDirection.Empty for bound empty aggregates * Implement connectFromBits in ChiselEnum (#1052) This is necessary to use ChiselEnum in aggregates where things are casted using .asTypeOf * Move Analog to experimental. More repackage cleanup - reduce differences with master. Cleanup chisel3 references. More chisel3 reference cleanup. * Fix wrong directionality for Vec(Flipped()) Create Chisel IR Port() in a way that Converter is happy with. Also add more extensive test suite for future-proofing. Close #1063 * Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Put BitPat back in chisel3.util More experimental motion - avoid multiple import definitions. Add experimental.FixedPoint alias Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Add Reset alias to core/package Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Repair IntelliJ's overly cleanliness. Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3 and deal with the subsequent fallout. Move Aggregate, Clock, Mem, Printf, Reg Move almost all chisel3.core definitions to chisel3 or chisel3.experimental Revive core package object to provide aliases for moved definitions. Cleanup package definitions; eliminate ambiguous implicits Move more definitions to experimental. Extract BaseModule, DataMirror, ExtModule, IO into their own files. Add EnumType definition to core package. Update deprecated messages to refer to correct object Move FixedPoint into the experimental package (but keep it in Bits.scala). Add missing implicits to core/package - compatibility Cleanup: update ScalaDoc references; remove unused imports Use common 3.2 version in deprecation warning Move Binding from core to internal. Optimize imports. Merge cleanup. Remove unused import Bump core deprecation to 3.3 Move DontCare back into Data.scala inside package internal Re-indent experimental/internal package code Move code back to original files - facilitate comparison with other branches Some code motion, update imports, minimize master differences Move exceptions up to chisel3 package object - they're part of the interface. More master diff minimization. Fix minor discrepancies with repackagecore-testbed * Remove redundant imports As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._` * Move the BaseModule object into the internal package.
2019-03-18Split #974 into two PRs - scalastyle updates (#1037)Jim Lawson
* Update style warnings now that subprojects are aggregated. Use "scalastyle-test-config.xml" for scalastyle config in tests. Enable "_" in method names and accept method names ending in "_=". Re-sync scalastyle-test-config.xml with scalastyle-config.xml * Remove bogus tests that crept in with git add * Add missing import.
2019-01-25WireDefault instead of WireInit, keep WireInit around (#986)Martin Schoeberl
2019-01-22Define Data .toString (#985)Richard Lin
toString on Data subtypes will now print the type and optionally binding information including literals and IO names as feasible.
2018-07-02Direct to FIRRTL (#829)Jack Koenig
Provide direct conversion from ChiselIR to FIRRTL. Provide Driver support for dumping ProtoBuf.
2017-08-17More of the bindings refactor (#635)Richard Lin
Rest of the binding refactor
2017-04-13Module Hierarchy Refactor (#469)Richard Lin
2016-11-21Restyle a lot of test code, mainly with regexducky
2016-09-07Fix bug in Printable FullName of submodule portjackkoenig
Printable was using HasId.instanceName to get full names of Chisel nodes. instanceName uses the parent module of the HasId to get the Component to use in calling fullName on the underlying Ref. Unfortunately this means that any reference to a port of a instance will leave off the instance name. Fixing this required the following: - Add Component argument to Printable.unpack so that we can call Arg.fullName directly in the Printable - Pass the currently emitting module as the Component to Printable.unpack in the Emitter - Remove ability to create FullName Printables from Modules since the Module name is not known until after the printf is already emitted This commit also updates the PrintableSpec test to check that FullName and Decimal printing work on ports of instances
2016-09-07Add Printable (#270)Jack Koenig
Printable is a new type that changes how printing of Chisel types is represented It uses an ordered collection rather than a format string and specifiers Features: - Custom String Interpolator for Scala-like printf - String-like manipulation of "hardware strings" for custom pretty-printing - Default pretty-printing for Chisel data types
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